2338 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 54, NO. 6, DECEMBER 2007 New Insights Into Single Event Transient Propagation in Chains of Inverters—Evidence for Propagation-Induced Pulse Broadening V. Ferlet-Cavrois, Senior Member, IEEE, P. Paillet, Senior Member, IEEE, D. McMorrow, Member, IEEE, N. Fel, J. Baggio, Member, IEEE, S. Girard, Member, IEEE, O. Duhamel, J. S. Melinger, M. Gaillardin, Student Member, IEEE, J. R. Schwank, Fellow, IEEE, P. E. Dodd, Senior Member, IEEE, M. R. Shaneyfelt, Fellow, IEEE, and J. A. Felix, Member, IEEE Abstract—The generation and propagation of single event transients (SET) is measured and modeled in SOI inverter chains with different designs. SET propagation in inverter chains induces significant modifications of the transient width. In some cases, a “propagation-induced pulse broadening” (PIPB) effect is ob- served. Initially narrow transients, less than 200 ps at the struck node, are progressively broadened up to the nanosecond range, with the degree of broadening dependent on the transistor design and the length of propagation. The chain design (transistor size and load) is shown to have a major impact on the transient width modification. Index Terms—Chains of inverters, digital single event transients, heavy ion and pulsed laser irradiation, propagation-induced pulse broadening (PIPB) effect, SET propagation, SET width. I. INTRODUCTION T HE propagation of Single Event Transients (SETs) is a growing concern for advanced digital circuits designed for use in radiation environments. Technology scaling has resulted in a greater sensitivity to single event upset (SEU), and has led to new failure modes, such as SET propagation and capture. De- pending on the location of the ion strike, voltage transients can propagate through the circuit and generate errors in clock trees in synchronous circuits, counters, and any digital chain termi- nating with a latch or a memory element [1]. Digital SET propagation has been explored previously through both simulation and experiment. Circuit and mixed- Manuscript received July 19, 2007; revised September 6, 2007. The work per- formed at the Commissariat à l’Energie Atomique (CEA/DIF) was supported by the French Ministry of Defence (MOD/DGA). The work performed at the Naval Research Laboratory and a part of the work performed at Sandia National Labo- ratories was supported by the Defense Threat Reduction Agency. The work per- formed at Sandia National Laboratories was supported by the U. S. Department of Energy. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the U. S. Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000. V. Ferlet-Cavrois, P. Paillet, N. Fel, J. Baggio, S. Girard, and O. Duhamel are with CEA/DIF, BP12, 91680 Bruyères-le-Châtel, France (e-mail: veronique. ferlet@cea.fr). D. McMorrow and J. S. Melinger are with the Naval Research Laboratory, Washington, DC 20375 USA. M. Gaillardin is with IMEP-ENSERG, 38016 Grenoble, France. J. R. Schwank, P. E. Dodd, M. R. Shaneyfelt, and J. A. Felix are with Sandia National Laboratories, Albuquerque, NM 87123 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2007.910202 mode simulations are irreplaceable tools for elucidating propa- gation mechanisms and analyzing variations in technology and design parameters. Recent experimental developments permit the determination of digital SET pulse widths using specifi- cally designed test vehicles. Those “indirect” approaches use latch cells to capture and characterize the propagating voltage transients [2]–[8]. A key advantage of these approaches is that they bracket the SET pulse width for the technology and design of interest. Recent experimental results, in both bulk and SOI technologies, reveal large distributions of pulse widths, with the widest pulses extending into the nanosecond regime [3]–[8]. The origins of these distributions are not yet understood. Related work has attempted to model and calculate SET widths from the current transients measured in single transis- tors. A simple “figure of merit” methodology for digital SETs in inverters is presented in [9]. In that approach, if the off-state NMOS is struck, the SET voltage width can be estimated from the duration of the generated current pulse at the level of the on-state PMOS current. A more sophisticated method is presented in [10]. In that approach, single transistor current transients simulated at different drain voltages are used to calculate the actual shape of SET voltage transients generated in inverter chains. SETs are not treated as rail-to-rail digital glitches, but rather as analog signals. In general, these studies reveal that the SET pulse widths, whether calculated using sim- ulations or estimated from the transient current in elementary transistors [9], [10], are found to be much shorter than those measured by the indirect experimental methods. The origin of the apparent discrepancy between the “indirect” measurements and “reconstruction” approaches requires addi- tional investigation. Transient currents in an isolated OFF-state transistor, for example, are measured while a fixed bias is ap- plied to the drain electrode. In single transistor measurements, since the bias is maintained by a supply voltage during the en- tire event, the transient current undergoes a rapid return to the initial equilibrium condition. As a consequence, the SET pulse width estimated from single transistor measurement will repre- sent a lower limit. In an inverter, in contrast, since the output po- tential is neither controlled nor maintained, the potential varies during the course of the event, thus potentially leading to longer SET pulses. It might be assumed that the discrepancy in SET pulse widths occurs because direct measurements do not take into account the voltage drop at the output of the inverter. The 0018-9499/$25.00 © 2007 IEEE