International Journal of Innovative Research in Computer Science & Technology (IJIRCST) ISSN (online): 2347-5552, Volume-11, Issue-2, March 2023 https://doi.org/10.55524/ijircst.2023.11.2.11 Article ID IRP1373, Pages 58-61 www.ijircst.org Innovative Research Publication 58 Verification of UART and I2C Protocols Using System Verilog Dr. Ch. Manohar Kumar 1 , Mr. G. Mahesh Babu 2 , Mr. A. Hemanth Chakradhar 3 , Mr. A.S.K. Pranav 4 , Mr. D. Sudheer 5 , and Mr. U. Alex Prince 6 1 Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India 2,3,4,5,6 Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree andPG Courses(A), Visakhapatnam, Andhra Pradesh, India Correspondence should be addressed to Dr. Ch. Manohar Kumar; manohar@gvpcdpgc.edu.in Copyright © 2023 Made Dr. Ch. Manohar Kumar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ABSTRACT- Design Verification in VLSI is the most important step in the product development process. It aims toconfirm that the system designed meets with the standards andrequirements of the system. Verification is the process ofchecking whether the designed system performs all the required functionality specified in the design by writing the test bench or verification environment that contains group ofclasses and modules which generates input stimulus to the system and the output from that design is compared with the expected output. A communication system has set of roles those are called protocols. UART is a serial communication protocol that is used when only two devices are needed to communicate and it uses peer to peer topology. I2C stands for Inter Integrated Circuit used for communication between master and slave in which more than one slave devices or memory can be connected to a master device. System Verilog has been primarily used for the verification purposes in VLSI because it has the features of Hardware Description Languages such as Verilog and VHDL, C and C++ and functional coverage, assertion coverage, constrained randomization and supports OOPs concepts. KEYWORDS- Verification, Protocols, UART, I2C, System Verilog. I. INTRODUCTION A. Verification in VLSI is Done in Two Stages Verification is the Predictive analysis that is done to make sure the design will carry out the specified input output function when manufactured [1]. Test: A production phase that verifies there are no manufacturing defects in the actual product that was created from the synthesized design. System Verilog has special features like randomization, functional coverage, assertions and use OOP features in test bench construction. Test bench is a group of classes or components where each component is responsible for performing a specific operation. i.e. generating stimulus, driving to the DUT, monitoring, comparing and scheduling different events like reset, main tasks etc. and those classes will be named based on the operation[9,10]. Figure 1: Block Diagram of System Verilog Test Bench