Impact of Trap Behavior in High-k/Metal Gate p-MOSFET with Incorporated Fluorine on Low-Frequency Noise Characteristics Tsung-Hsien Kao 1* , San-Lein Wu 2 , Chung-Yi Wu 2 , Yean-Kuen Fang 1 , Po-Chin Huang 1 , Chien-Ming Lai 3 , Chia-Wei Hsu 3 , Yi-Wen Chen 3 , Osbert Cheng 3 and Shoou-Jinn Chang 1 1 Institute of Microelectronics and Department of Electrical Engineering, Advanced Optoelectronic Technology Cen- ter, Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan 701, Taiwan 2 Departments of Electronic Engineering, Cheng Shiu University, Kaohsiung 833, Taiwan 3 Central R&D Division, United Microelectronics Corporation (UMC), Tainan 744, Taiwan Phone: +886-6-2757575 ext.62391 Fax: +886-6-2671854 * e-mail: q18011247@mail.ncku.edu.tw Abstract Impact of Fluorine (F) implantation on 1/f noise and random telegraph noise (RTN) characteristics in High-k/Metal Gate (HK/MG) pMOSFETs are investigated. In addition, incorporation of F has been identified as an effective method for passivating oxygen vacancies and defect sites and controlling V T in PMOS. Then RTN and 1/f results found that irrespective of the implanted dose, HK/MG devices with F implanted exhibited lower slow oxide trap densities to the control device. 1. Introduction Low-Frequency (LF) noise is a useful characterization tech- nique for the study of slow oxide or border traps in the gate die- lectric of a MOSFET. For sub-28-nm era, issues of direct gate tunneling, poly-gate depletion, gate sheet resistance, boron pene- tration, and Fermi level pinning [1] become the severe obstruc- tions for performance improvements. To eliminate these problems, high-permittivity (HK) materials and metal gate (MG) electrodes have extensively replaced conventional SiO 2 gate oxide and poly-gate, respectively. However, fabricating a metal gate p-type metal–oxide–semiconductor (PMOS) transistor with low threshold voltage (V T ), especially with a small equivalent oxide thickness (EOT), is crucial in gate-first integration owing to the presence of various oxygen vacancies and defect sites in the HK gate dielec- tric. Recently, incorporation of F has been identified as an effec- tive method for passivating oxygen vacancies and defect sites [2] and controlling V T in PMOS [3]. However, to obtain large V FB shift with minimized EOT penalty in HK/MG pMOSFETs, alu- minum (Al) ion implantation (I/I) technology was implemented and identified as an effective approach for effective work function (EWF) modulation without EOT increasing and complicated pro- cess [4]. On the other hand, the low frequency noises including 1/f noise and RTN in device drain currents (I D ) has been used for many decades as an indicator of device performance and reliabil- ity, which is attributed to the random trapping/detrapping process of signal or multiple traps in the gate dielectric, results in two discrete current levels in the time domains. By characterizing of RTN as a function of temperature or bias dependence, the energy level, capture and emission kinetics, and spatial location of traps can be obtained. Especially, the analysis on RTN in HK/MG stacks devices to determine whether an oxide trap leading to RTN is located in high-k layer or in interfacial layer (IL) and then to characterize such a trap will be beneficial to develop new process flow evolution. In this paper, we present the correlation between RTN and 1/f noise parameters in HK/MG stacks pMOSFETs with F into the HK gate dielectric and Al I/I. 2. Device Structure and Experiment For the experimental work, all pMOSFETs devices were fabricated using 28 nm gate-first (HK/MG) technology. The gate dielectrics consist of a 1 nm thermal-grown SiO 2 as an IL, fol- lowed by a 2.5 nm atomic layer deposition on HfO 2 HK film. In F channel implantation experiments, 2 × 10 15 cm -2 (device A) and 5 × 10 15 cm -2 (device B) doses of F were implanted at 10 keV through a 4-nm-thick layer of sacrificial oxide, and then oxide mask was removed and subsequently fresh core oxide was grown. A rapid thermal spike (RTP) annealing was performed at 930˚C to manipulate the F distribution profile after implantation. A 10 nm radio-frequency PVD TiN was deposited as gate metal, Al ion implantation through TiN layer was performed at 1.2 keV with dose of 5 × 10 15 cm -2 . For comparison, HK/MG pMOSFETs without F implanted were also fabricated and labeled as control device. 3. Results and Discussion Fig. 1 shows the drain current (I D ) as a function of drain volt- age (V D ) for all HK/MG pMOSFETs. Approximately 4 and 11% I D enhancement obtained for device A and B, respectively, as compared with the control device at a fixed gate overdrive, V G - V T = -0.8 V, and V D = -1.0 V. The V T for device A, B, and the control are -0.51 V, -0.48 V, and -0.55 V, respectively in Fig. 2. The results indicated that F implanted, make a decline in the number of interface traps. F is thought to segregate at the HfO 2 /SiO 2 and SiO 2 /Si interfaces and effectively to passivate interface charge-trapping sites, consistent with the higher PMOS V FB that is associated with a lower interface state density and fewer oxygen vacancies [5]. To investigate the impact of F im- planted on 1/f noise of HK/MG devices, the normalized drain current noise spectral density S ID for all HK devices taken from the average of six devices biased at different gate overdrive volt- ages are presented as Fig. 3. All devices show typical 1/f noise type with the frequency exponent close to unity for all gate over- drives. The noise level in devices A and B is observed to be sig- nificantly lower than the control with no F implanted, which im- plies high-k layer has lower trap density. The normalized drain current noise spectral density (LS ID /I D 2 ) and the transconductance to drain current squared (g m /I D ) 2 as function of drain current are plotted in Fig. 4 to confirm the physical mechanism of 1/f noise. The LS ID /I D 2 was extracted at f = 25 Hz for all devices. The LS ID /I D 2 curve of all devices shows cannot follow this trend at high current with (g m /I D ) 2 , which imply that either of the correlat- ed mobility fluctuation (Δμ) or source/drain (S/D) series re- sistance is major noise mechanism and need to be clearly clarified [6]. Using Fig. 5, all devices shows (V G - V T ) -m with m ~ 0.97 for all devices, which highlights that the noise contribution of the series resistance to the overall noise is negligible. In order to fur- ther evaluate the parameters of 1/f noise model on all devices, the normalized input-referred voltage noise spectral density (LS VG ) as a function of the V G - V T is shown in Fig. 6. As expected, all de- vices show two distinct regions in the associated LS VG . In region I ( 0.2 G T V V V   ), the LS VG is independent of V G - V T , which indicate a signature of number fluctuations. In region II ( 0.2 G T V V V   ), a pronounced LS VG dependence on V G - V T indeed proves that correlated mobility fluctuations were involved. Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials, Tsukuba, 2014, - 50 - PS-3-4 pp50-51