Reliability Analysis of Bumping Schemes under Chip Package Interaction Sri Ramakanth Kappaganthu 1 , Aditya Karmarkar 1 , Xiaopeng Xu 2 , Karim El Sayed 2 , Ibrahim Avci 2 , Vikas Chawla 2 , Bikash Mishra 2 , Andrey Kucherov 2 , Weixing Zhou 2 , Mark Johnson 2 , Pratheep Balasingam 2 1 Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh 500032, India 2 Synopsys, Inc., Mountain View, CA 94043, U.S.A. ABSTRACT Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties. INTRODUCTION Packaging and assembly operations for advanced electronics involve high temperature steps that introduce thermomechanical stresses in the package due to material property differences. Chip package interaction (CPI) becomes a significant cause of reliability concern due to these residual stresses [1], [2]. Previous studies have revealed that the stress concentrations caused by CPI can lead to low-k dielectric cracking, interlayer delamination and bump failures [3], [4]. Chip package interaction has been observed to strongly depend on the bumping scheme that includes the conventional bumping configuration with spherical solder bumps, and new bumping configurations with copper pillar bumps [5], [6]. Hence, in order to design a robust electronics package, it is important to analyze the reliability of different bumping schemes under chip package interaction. In this paper, reliability analysis is performed for three different bump configurations under typical chip package interaction. These bumping configurations consist of spherical solder bump, copper pillar with a contact pad and copper pillar landing directly on the substrate trace. A sequential submodeling technique is used to examine the mechanical stress evolution at each package assembly step [7]. Underfill material properties are varied to examine their impact on the mechanical stress distribution around bumps. An advanced FEM based 3D TCAD simulator is employed to perform the sequential package assembly simulation [8]. SIMULATION METHODOLOGY A. Finite Element Model An advanced electronics package is a large structure that consists of multiple elements at various length scales. These scales represent a difference of about five orders of magnitude from the package to backend level. To effectively simulate the package assembly flow at these length scales, a multi-level multi-scale submodeling simulation approach is used. A two stage submodeling simulation that consists of a global model and a submodel is used in this paper. Fig. 1 (A) shows the submodeling simulation routine used here. The global model is approximated as a thin 3D diagonal strip extracted from a package structure as shown in Fig. 1 (B). The submodel simulates the bump and the surrounding region with back-end passivation layers. Fig. 1 (C) shows various geometries and dimensions in the global model. Fig. 1: (A) Submodeling routine; (B) Diagonal strip model; (C) Chip package stack near die corner. Fig. 2: (A) Solder bump; (B) Cu pillar; (C) Cu pillar on trace; (D) Far back end layers; (E) Averaging volumes in bump and solder joint; (F) Averaging volume in ELK Fig. 2 shows the three different bumping configurations analyzed in the submodel, along with the back-end layers. Fig. 2 (A) shows a bump structure that uses a spherical solder bump, Fig. 2 (B) shows a bump structure with a copper pillar bump and Fig. 2 (C) shows a bump structure where the copper pillar bump lands directly on the substrate trace. Fig. 2 (D) shows a close-up view of the far back end layers indicated by the dotted rectangle in Fig. 2 (B). The far back end layers are the same in all the bumping schemes. Black boxes in Fig. 2 (E) indicate the locations where stresses are averaged in 3 978-1-4799-5018-8/14/$31.00 ©2014 IEEE 151