979-8-3503-7952-5/24/$31©2024 IEEE Design and Performance Analysis of FinFET Based 12T SRAM Cell 1 Chintada Lokesh UG Student ECE Department GMR Institute of Technology Rajam, India 21341A0431@gmrit.edu.in 2 Burle Ram Prasad UG Student ECE Department GMR Institute of Technology Rajam, India 21341A0427@gmrit.edu.in 3 Dannana Leelavardhan UG Student ECE Department GMR Institute of Technology Rajam, India 21341A0434@gmrit.edu.in 4 Etcherla Prem Kumar UG Student ECE Department GMR Institute of Technology Rajam, India 21341A0448@gmrit.edu.in 5 Bevara Satyam Naidu UG Student ECE Department GMR Institute of Technology Rajam, India 21341A0420@gmrit.edu.in 6 Jami Venkata Suman ECE Department GMR Institute of Technology Rajam, India venkatasuman.j@gmrit.edu.in Abstract— Power optimization has become increasingly critical in the VLSI industry due to the rising density of memory systems, which leads to higher power consumption. Static RAM (SRAM) cells are particularly affected by this issue. A significant contributor to power consumption is the leakage current in transistors. Therefore, decreasing power consumption in each memory cell is essential. This paper focuses on optimizing the power of various 12T SRAM cells through an analysis of the transistor stacking technique. Instead of relying a single larger transistor, two smaller transistors are connected in series and switched off together. This configuration reduces leakage current, thereby decreasing power consumption in SRAM cells. The power usage of SRAM cells in presence and absence of the stacking method, is evaluated under different voltage conditions and performed simulations in Cadence Virtuoso. Keywords—Stacking, SRAM, FinFET, power consumption I. INTRODUCTION The design of semiconductor devices has advanced significantly with the development of Fin Field-Effect Transistors (FinFETs), especially as the market shifts to transistors that are more compact and power-efficient. As device dimensions decrease to nanometer scales, conventional planar transistors have encountered difficulties in managing leakage currents and short-channel effects [1]. Due to these difficulties, FinFETs which provide enhanced performance, power efficiency, and scalability have been developed and adopted [2]. FinFETs are a type of 3D transistor where the conducting channel is wrapped by a thin, fin-shaped silicon structure. Unlike conventional planar transistors, which have a single gate, FinFETs typically feature multiple gates that surround the fin on three sides [3]. This multi-gate configuration allows for better control over the channel, significantly reducing leakage currents and improving the overall performance of the device. The enhanced gate control also minimizes the short channel effects that plague traditional transistors at smaller nodes [4]. The ability of FinFET technology to function at lower voltages while maintaining great performance is one of its fundamental features. Because of this, FinFETs are especially appealing for applications like data centers, high- performance computing, and mobile devices where power efficiency is critical. In addition to extending battery life in portable devices, FinFET’s lower power consumption helps control heat dissipation in closely spaced circuits, enabling higher integration densities [5]. FinFETs provide enhanced switching speeds and decreased variability in addition to power efficiency, which is critical for scaling to advanced technology nodes like 7nm and beyond [6]. Modern CPUs and memory components are built using FinFETs because of their reliable performance at these scales [7]. FinFETs are predicted to be crucial in enabling future miniaturization and performance improvements in electronic devices as the semiconductor industry pushes the limits of Moore's Law [8]. By offering better control over leakage currents and short- channel effects, FinFET technology overcomes the drawbacks of conventional planar transistors and produces notable gains in performance and power efficiency. FinFETs are expected to stay a mainstay of contemporary semiconductor design as the market develops, spurring innovation in a variety of applications from high- performance computing systems to mobile devices [9]. II. LITERATURE SURVEY In [9], the power optimization analysis of different SRAM cells using transistor stacking technique was well discussed what is basic conventional SRAM and working of SRAM cell. It also discusses what is stacking technique and the calculation of power consumption of various SRAM cells with stacking method and without stacking method in this paper they performed power calculations for different supply voltages. The FinFET technology based low power SRAM cell design for embedded memory was well discussed [10]. The advantages of using FinFET technology compared to CMOS 2024 IEEE International Conference on Intelligent Signal Processing and Effective Communication Technologies (INSPECT) | 979-8-3503-7952-5/24/$31.00 ©2024 IEEE | DOI: 10.1109/INSPECT63485.2024.10896024 Authorized licensed use limited to: National Institute of Technology Andhra Pradesh. Downloaded on February 28,2025 at 01:18:57 UTC from IEEE Xplore. Restrictions apply.