IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 6, JUNE 1995 715 Programmable CMOS Switched-Capacitor Biquad Using Quasi-Passive Algorithmic DAC’ s Nuno Paulino, JosC E. Franca, and F. P. Martins Abstract-This paper describes an electrically programmable switched-capacitor (SC) biquad using quasi-passive algorithmic digital-to-analog converters (DAC’s). Since only two equal- valued capacitors are needed for programming each capacitance value, the proposed technique offers compact, cost-effective programmability when compared to traditional programming techniques employing binary-weighted capacitor-arrays (C- arrays). A demonstration prototype chip realized in a 1.2pm CMOS double-metal double-poly technology, and which implements an 8 b programmable SC biquad giving a wide range of lowpass, bandpass and highpass filtering functions, occupies an active area of only 0.38 mm’. I. INTRODUCTION IELD programmable IC’s are receiving increased atten- F tion prompted by the need of realizing with the shortest possible delay time a variety of dedicated functions in custom specific IC applications [I]. Current research efforts have been primarily directed towards producing field programmable digital IC’s with increased functionality and efficiency, but it is envisaged this trend will also expand into the area of field programmable analog IC’s [2]. Although SC circuits are particularly advantageous for programming analog functions on-chip, previous implementations employing digitally con- trolled binary-weighted C-arrays (e.g., [3]-[5]) have required large areas of silicon and hence high cost of manufacturing. In this paper a new technique is proposed for electrical programmability of SC biquads. It is based on the concept of charge-programmability realized using quasi-passive al- gorithmic digital-analog converters (DAC’s), and leads to a significant reduction of the overall capacitor area needed for IC implementation and thus lower cost of manufacturing. Besides this introduction, the paper comprises five additional sections. Section I1 looks at the capacitance programming techniques of SC branches from the viewpoint of digital-to- analog converters, in particular the traditional binary-weighted C-array multiplying DAC as well as the proposed cost- effective algorithmic quasi-passive DAC. Section 111 describes the architecture of the programmable SC biquad using quasi- passive DAC’s, and presents the systematic design method- ology yielding the digitized coefficients needed for digital programming of each relevant SC branch. The design and Manuscript received June 20, 1994; revised November 16, 1994. This work was jointly funded by the Ministry of Defense under the European EUCLID RTP 2.9 project and the Junta Nacional de Investiga@o Cienthca e Tecnol6gica under the PUZZLE project (PBICIC/TIT/1240/92). N. Paulino and J. E. Franca are with Instituto Superior Tecnico, Center for Microsystems-Integrated Circuits and Systems Group, 1096 Lisboa Codex, Portugal. F. P. Martins is with Ministtrio da Defesa Nacional, Dep6sito Geral de Material de TransmissBes, Linda-a-Velha, Lisboa, Portugal. IEEE Log Number 9408449. experimental characterization of an 8-b programmable SC biquad realized using a 1.2pm CMOS technology are given in Section IV. The conclusions are drawn in Section V. 11. ELECTRICALLY PROGRAMMABLE SC BRANCHES The traditional solution for electrical programmability of SC branches consists of replacing the associated capacitor by a binary-weighted C-array which can be programmed to a resolution of N-bits. In an SC network with K capacitors, a total of K x 2N capacitors and K x N digital lines are required to program independently every capacitor and thus achieve full programmability of the SC network. Despite its simplicity, this solution needs high component count (both of capacitors and switches) and the number of control signals increases proportionately to the resolution of the C-arrays. In order to reduce the capacitance spread as well as the number of capacitors and switches associated with the binary- weighted C-arrays we can utilize instead the quasi-passive algorithmic DAC illustrated in Fig. l(top), with positive gain [6]-[8]. In the timing diagram represented in Fig. l(bottom) each one of the switching waveforms S and T have N pulses synchronized with the N bits of the programming digital word where bN-1 is the most significant bit (MSB) and bo is the least significant bit (LSB). The pulses SOC (start of conversion) and EOC (end of conversion), respectively, determine the duration of the conversion process. For each sample of the input signal V,, the conversion starts by resetting capacitor Clb with pulse SOC. Then, if the LSB of the programming digital word is bo = 1, the first S pulse connects capacitor C1, to K; in the subsequent T pulse, capacitor C1, is connected in parallel with Clb such that the charge qa = Clavi divides between both capacitors and yields qb = (C1,/2) V,. If bo = 0, then capacitor C1, samples ground during the first S pulse and hence during the subsequent T pulse no charge flows into capacitor Clb, i.e., qb = 0. By repeating similar operations during the next S and T pulses capacitor Clb accumulates the results of consecutive divisions by two of the charge sampled into C1,. After all bits have been processed pulse EOC forces the final charge accumulated into capacitor Clb to be transferred to the integrating feedback capacitor C, to produce an output voltage. For simplicity, we designate x = c1, = Clb as the equivalent capacitance value of the programmable SC branch. Hence, for a given N-bit programming digital word W,, the effective multiplying capacitance value is given by N-1 X[WZ] = (bn2”-N)X. (1) n=O 0018-9200/95$04,00 0 1995 IEEE