Leakage Minimization of Nano-Scale Circuits in the Presence of Systematic and Random Variations*† Sarvesh Bhardwaj Computer Science and Engineering Arizona State University sarvesh.bhardwaj@asu.edu Sarma B.K.Vrudhula Computer Science and Engineering Arizona State University sarma.vrudhula@asu.edu ABSTRACT This paper presents a novel gate sizing methodology to mini- mize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The exist- ing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the ob- jective function is O(|N | 2 ) and that of evaluating the delay constraints is O(|N | + |E|) for a circuit with |N | gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids—Optimization General Terms Algorithms, Design, Performance Keywords Leakage, Statistical, Optimization, Geometric Programming 1. INTRODUCTION The lack of process uniformity in the semiconductor man- ufacturing has caused variability to become the primary cause of concern for nanometer scale CMOS design. Sig- nificant research efforts have focused on understanding the causes and effects of spatial variations [24, 23, 13, 1, 10, 15, 26]. The variations are caused by either global effects [24] * Any opinions, findings, and conclusions or recommenda- tions expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Sci- ence Foundation. This work was carried out at the NSF’s State/Industry/University Cooperative Research Centers’ (NSF-S/IUCRC) Center for Low Power Electronics (CLPE). CLPE is supported by the NSF (Grant #EEC-9523338), the State of Arizona, and an industrial consortium. This work was also supported by NSF through grant #CCR-0205227. † Full version of this paper is available at:http://veda.eas.asu.edu/papers/bhardwaj-dac05.pdf Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2005, June 13–17, 2005, Anaheim, California, USA. Copyright 2005 ACM 1-59593-058-2/05/0006 ...$5.00. such as mask imperfections and lens aberration, or local ef- fects [9] such as layout pattern variations. As shown in [1], for 30% variations in the circuit delay there can be 20X variations in the leakage current. Various design techniques for leakage reduction such as transistor stacking [12], sleep transistor insertion [8], body biasing [14] and driving the circuit into a minimum leakage sleep state have been proposed in the past. The power savings accrued by these techniques can be supplemented by gate sizing and dual-threshold voltage (Vt ) assignment [29, 20, 7, 21]. Traditional deterministic gate sizing [19, 3] and dual-Vt as- signment techniques [6] can be classified into two major cat- egories: discrete optimization approaches and non-linear op- timization techniques. In discrete optimization techniques, starting with an initial feasible implementation (say, all gates assigned the smallest gate size and low-Vt ), the gates to be sized up (or assigned a higher Vt ) are selected based on their sensitivities. In every iteration, the timing constraints are checked for any possible violations. These techniques pro- vide good solutions but because of large number of feasible solutions, it is difficult to guarantee the optimal solution. Non-linear programming based techniques use suitable mod- els for the objective function (power) and the constraints (delay) to formulate an optimization problem. This prob- lem can then be solved using non-linear optimization tech- niques [5, 19] to obtain an optimal solution. In the presence of process variations, the parameters have to be modeled as random variables. Due to this, there has been an increased interest in techniques for statistical anal- ysis [27] and optimization of circuit performance. A number of statistical optimization methods ([4, 25] to name a few) have been proposed in the past. These approaches are pri- marily based on evaluating the yield (probability that a de- sign has acceptable performance) as the integral of the joint probability distribution (jpdf) of the circuit performance φ over its acceptability region, A φ . Once an approximation to A φ is obtained, the design center is moved to the interior of A φ such that the yield is maximized. Because of their high computational complexity, these techniques are suit- able only for small circuits where the number of design pa- rameters is small. Another class of statistical optimization techniques [22, 17] have been proposed recently. These tech- niques are similar to the deterministic optimization tech- niques described above but they model the variability in the device parameters. In this paper we present a statistical optimization ap- proach based on modeling the statistics (mean and second moment) of leakage and delay as posynomial functions [16] of nominal gate sizes. A function of mean and variance of leakage is minimized subject to constraints on α-percentile of the delay. The posynomial functions can be transformed into convex functions by a variable transformation. This 32.4 541