73 978-1-4673-2771-8/12/$31.00 ©2012 IEEE IEEE Asian Solid-State Circuits Conference November 12-14, 2012/Kobe, Japan 2-5 A 0.2V 16Kb 9T SRAM with Bitline Leakage Equalization and CAM-assisted Write Performance Boosting for Improving Energy Efficiency Bo Wang 1,2 , Truc Quynh Nguyen 1 , Anh Tuan Do 1 , Jun Zhou 2 , Minkyu Je 2 and Tony T. Kim 1 1 VIRTUS, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2 Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore Email: bwang6@e.ntu.edu.sg, thkim@ntu.edu.sg Abstract—An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM- assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8× at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS (MTCMOS) SRAM array implemented with higher-V th (HVT) devices. The inserted tiny CAM conceals the slow data development after data flipping, and therefore improves overall operating frequency in the near threshold region. A 16Kb SRAM test chip was fabricated in 65nm CMOS technology and showed the minimum energy of 0.33 pJ at 0.4V. I. INTRODUCTION Ultra-low power SRAMs have been increasingly demanded due to their wide applications in power- or energy- constrained SoCs [1],[2]. However, ultra-low voltage operation for ultra-low power generates various issues. With supply voltage scaling, degraded bitline sensing margin is more challenging due to the significant influence of bitline leakage current on sensing. An 8T coupled SRAM cell [3] is proposed to inject identical leakage current into the differential bitlines, which eliminates the differential offset voltage due to the bitline leakage current. Decoupled SRAM cells [4]-[6] have been widely employed thanks to the improved read static noise margin (SNM) and the boosted bitline sensing margin compared to the conventional 6T SRAM cell. In addition, techniques tackling read bitline (RBL) leakage have been proposed to enhance sensing margin. In [6], the leakage current is forced to flow from the unselected cells to the RBLs regardless of the data stored, which improves the sensing margin. However, the 10T SRAM cell to implement data-independent bitline leakage leads to a large increase in the layout. Energy minimization is another design challenge for ultra- low power SRAMs. Voltage scaling decreases the active energy quadratically. However, the long data retention period makes SRAM energy in idle mode is as important as the active energy. To optimize the energy portion on retention cycle, leakage current minimization is preferred [7]. Generally, lower-V th (LVT) devices are used in the critical paths (read paths) to achieve high performance while higher-V th (HVT) devices are adopted in the non-critical paths (non-read paths) to suppress the leakage. However, for ultra-low voltage operation, this MTCMOS implementation could nullify energy efficiency due to substantially slower write with HVT devices than read with LVT devices. In this paper, we present a circuit technique for equalizing RBL leakage with an additional discharging path in the proposed 9T SRAM cell. This enables constant RBL leakage and achieves augmented bitline swing. We also propose a CAM-assisted performance improvement technique to ameliorate the performance difference between slower write and faster read in the near threshold region. This enhances operating frequency and consequently improves the energy efficiency. The details of the proposed equalization technique and the CAM-assisted technique are discussed in Section II and Section III, respectively. The measurement results are presented in Section IV. Section V draws the conclusions. II. PROPOSED 9T SRAM BITCELL WITH A BITLINE LEAKAGE EQUALIZATION TECHNIQUE A. 9T MTCMOS SRAM bitcell Fig. 1 depicts the proposed 9T SRAM bitcell and the layout. The read port consists of three NMOS LVT transistors (M7, M8 and M9) for realizing the equalized bitline leakage. The write access paths and the data storage latch are implemented with HVT devices for leakage reduction. A read operation starts by enabling the read wordline (RWL) and is Fig. 1. Schematic and layout of the proposed 9T SRAM bitcell with equalized bitline leakage.