Abstract—In this paper an efficient traffic control system is designed using Mealy finite state machines. The effects of state encoding schemes like sequential encoding, gray encoding and One-Hot encoding are compared on the basis of size of synthesized circuit. Coding of the design is done in Verilog HDL and the design is tested and simulated on Spartan-3 xc3s400 FPGA development kit. The sensors are added as input to the controller for emergency conditions like ambulance etc. This system is also capable to change the timings of traffic signals according to the density of vehicles on the roads. The design has several benefits over ordinary traffic light controllers built with microcontrollers or Programmable logic controller such as simple structure, high reliability, low costs, ease in installation and maintenance. The design of adaptable traffic control system is carried out for a chowk consisting of five roads. Each road is divided into main road (for straight movement) and cross road (for crossing). To some extent, traffic jam, unreasonably latency time of stoppage of vehicles, emergency vehicles like ambulances, VIP movement or forcibly passing is solved. So, this system carries a broader application prospect. Index Terms—FPGA, DSP, FSM, HDL, Xilinx, ASIC, LUT I. INTRODUCTION Conventional traffic control systems has two major drawbacks: First, [1] due to lack of adjustments in timings of traffic signals, the traffic has to wait a long on the lane with few vehicles while on same lane, the traffic cannot pass through in short time due to rush on lane. Second, [2] there is no provision of movement of emergency vehicles like ambulance and fire brigades etc. In rush hours these emergency vehicles have to wait a long and results in human and financial loss. So, there is a need to develop a secure, fast and reliable traffic control system capable to control the vehicular traffic in rush hours without a need of traffic sergeant. In this paper, we have developed a real traffic control system using Mealy state machines. The design is implemented in Verilog HDL Hardware Description language. We use different modeling styles to implement state machines to improve the readability of code and to increase the speed. The effect of state encoding on the size of synthesized circuit is also realized. The implemented architecture is then tested for the validation of the design on Spartan-3 xc3s400 FPGA Development Kit. A. Field Programmable Gate Array (FPGA) Field Programmable Gate Array (FPGA) is a Manuscript received April 9, 2012; revised May 25, 2012. M. A. Qureshi and A. Aziz Qureshi are with Islamia University of Bahawalpur, Pakistan (e-mail: ali.qureshi@ iub.edu.pk, abdul.aziz@ iub.edu.pk). reconfigurable hardware platform useful for the implementation of high digital functions. Using fixed point, parallel computational structures, FPGA provides computational speeds as much as 100 times greater than those possible with Digital Signal Processors (DSP). The extremely fast computational capability of FPGAs allows a few microseconds for real-time computation of algorithms in spite of their complexities. Furthermore, as DSPs, FPGAs are very low cost components [3][4]. Xilinx Spartan-3 FPGAs are ideal for low-cost, high-volume applications and are targeted as replacements for fixed-logic gate arrays. The Spartan-3 FPGA is not only available for a very low cost, but it integrates many architectural features associated with high-end programmable logic. This combination of low cost and integrated features has made it an ideal replacement for ASICs (Application Specific Integrated Circuits) [5]. B. Finite State Machines (FSM) Finite State machines are used to generate sequence of control signals. There are two types of state machines: Mealy machines and Moore machines. The difference between Mealy and Moore machines relies in the methods of output generation. In Moore machines, outputs are function of current state. This means that whenever state changes, the output also changes. In Mealy machines, outputs are function of both input and current state. A state machine can be divided into three parts: State register, Next-State Logic and Outputs. It is necessary to model each part of the state machine in Verilog [6]. C. State Machine Modeling Style We can model each part of the state machine independently or by combining parts into one section. Different modeling styles of state machines are shown in Table I [7]. TABLE I: STATE MACHINE MODELLING STYLE Style State Register Next-State Logic Output Logic 1 Separate Separate Separate 2 Combined Combined Separate 3 Separate Combined Combined 4 Combined Combined Combined 5 Combined Separate Combined In the first style, each of the part of FSM is modeled in a separate always block. This style is modular in nature and easiest to maintain. The size of code increases in this modeling style. In second style, next-state logic and state register are combined. As Next-state logic and state register are strongly A Verilog Model of Adaptable Traffic Control System Using Mealy State Machines M. Ali Qureshi, Abdul Aziz, and S. Hammad Raza 400 International Journal of Computer and Electrical Engineering, Vol. 4, No. 3, June 2012