Robust Full On-Chip CMOS Low Dropout Voltage Regulator with Active Compensation Zared Kamal Electrical Engineering Department Faculty of sciences and technology Fez, Morocco zaredk@hotmail.com Qjidaa Hassan Department of Physics Faculty of sciences Dhar El-Mehraz Fez, Morocco qjidah@yahoo.fr Zouak Mouhcine Electrical Engineering Department Faculty of sciences and technology Fez, Morocco doyen@fst-usmba.ac.ma Abstract This paper present a full on-chip and area efficient low dropout voltage regulator(LDO), exploiting the nested miller compensation with active capacitor (NMCAC) to eliminate the external capacitor and active feedback resistors to reduce the chip area. The external capacitor is removed allowing for greater power system integration for system on-chip applications. The idea has applied to stabilize a 1.6 V, 50 mA Low dropout regulator. Using the proposed techniques the regulator LDO works with a supply voltage as low as 1.8 V and provides a load current 50 mA with a dropout voltage of 200 mV and output variation 4 mV when a full load step 0-50 mA is applied. It designed in 0.18 μm CMOS technology. Keywords Low dropout, MOSCAP, NMCAC, Active feedback, MOS compensation, low-voltage regulators, system on chip, regulators. I. INTRODUCTION Over the last decade, power management in integrated circuit has become an increasingly important design consideration for numerous products, especially those relying on battery power. Complicating the power management situation, as more features get integrated into products, the number of required voltage supplies increases. power management utilizing multiple local on-chip voltage regulators is a very promising approach in system-on-chip development [1][2]. The latest generation of LDOs offer the optimum answer for powering circuitry in many of the portable device applications such as cell phones, PDAs, pagers, notebooks, cameras and other handheld portable systems where high performance power supply circuits are required. In fact, they can provide regulated and accurate supply voltages for noise sensitive analog blocks, and they are often arranged in series to switching regulators to remove the inherent noise produced by the switching activity[4][7]. These advantages makes LDO widely used in portable systems, especially in RF circuitry To increase battery-life and to achieve better power efficiency. Unfortunately, the tradeoff between stability and dropout voltage of linear regulators makes uncompensated LDOs potentially unstable. The conventional LDO locates the dominant pole at very low frequency at the output to achieve the frequency compensation and provide a good dynamic performance, a large off-chip capacitor at LDO output, generally about 0.47 μF to 4.7 μF for 100 mA LDO [1],[3][8]. The large off-chip capacitor occupy a large chip area, and it is difficult to integrate multiple LDOs on a single chip. In order to design a full on-chip LDO regulator, the number of compensating capacitors must be minimized[3] [5],[7]. Different methods have been introduced recently to improve the performance of full on-chip LDO. In [4], the proposed LDO utilize a damping-factor control frequency compensation. The regulator is based on a multistage amplifier, and provide an output voltage of 1.8 V, a maximum output current of 150 mA and 108 mV of line regulation. however, the overshoots at the output of LDO proposed in [4] is too large (900 mV), and the settling time is about 5 μs. , it is not acceptable for SoC applications. In [6], the proposed structure improve a good stability, a high dc loop gain, but a problems still remain in this design. The overshoot is about 350 mV, the PSRR at 1 KHz is -40.6 dB. Moreover the complicated Miller frequency compensation is needed [4-6]. The nested Miller 978-1-4799-0792-2/13/$31.00 ©2013 IEEE