A 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter Thomas B. Cho and Paul R. Gray Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Abstract This paper describes a 10-bit, 20-MS/s pipeline A/D converter implemented in 1.2-μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include operation on a 3.3 V power supply, optimum scaling of capacitor values through the pipeline, and digital correction to allow the use of dynamic comparators. Measured perfor- mance includes 0.6 LSB of INL, 59.1 dB of SNDR for 100 kHz input at 20 MS/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB. I. Introduction The power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes a power-optimized 10-bit pipeline A/D converter that achieves ≈1.67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s. The pipelined configuration offers major advantages in achieving lower power dissipation in that the use of digital correction allows the relaxation of the comparator offset requirement, to the point that purely dynamic circuitry can be used to perform the comparator function. A block diagram of a typical pipeline A/D converter is shown in Fig. 1. It consists of a cascade of N identical stages in which each stage performs a coarse quantization (usually 1 to 3 bits), a D/A function on the quantization result, subtraction, and amplification of the remainder. A sample/hold (S/H) func- tion in each stage allows all stages to operate concurrently, giving very high throughput. Fig. 1 illustrates the particular configuration of interest here in which the D/A, subtraction, amplification, and S/H functions are performed by a switched capacitor circuit. The D/A function is performed by an array of equal capacitors. When the input signal is applied, each stage samples and quantizes the signal to its per-stage resolu- tion of B+1 bits, subtracts the quantized analog voltage from the signal by connecting the bottom plate of each capacitor to ±Vref or 0, and passes the residue to the next stage with amplification for finer conversion. One extra bit resolved in the flash A/D block allows the comparator offset to be within ±Vref / 2 B+1 as in [1,2]. In this implementation, the per-stage resolution (B+1) is chosen to be 2 bits, giving one bit of effective resolution after digital correction. The input signal to the first stage is sampled simultaneously by the switched capacitor amplifier and by the dynamic compara- tors of the flash A/D. This is made possible by the fact that digital correction allows comparator errors up to 1/4 full scale without degradation of linearity or SNR. The overall pipeline contains 9 2-bit flash quantizers and 8 interstage amplifiers. II. Power Reduction Strategies Reduction of power dissipation was achieved in this imple- mentation through several means. Use of lower power sup- ply voltage introduces several design issues, but results in substantial power savings. It also permits compatibility with the lower supplies used in more advanced scaled digital technologies. The power dissipation of the op amps in the pipeline is determined by the capacitive loading of each. Power can be substantially reduced by using the minimum possible value of capacitance at each point in the pipeline, as dictated by kT/C considerations. These design approaches are discussed in more detail in the following sections. B+1 bits B+1 bits B+1 bits STAGE STAGE STAGE + - op amp Vout Vref Vin Cs = 2 B x C Ci = C B+1 bits flash C C A/D D/A Interstage Amplifier -Vref Vin 1 N-1 N Fig. 1. A typical pipeline A/D converter architecture.