1292 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 12, DECEMBER 1998 JiffyTune: Circuit Optimization Using Time-Domain Sensitivities Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandu Visweswariah, Senior Member, IEEE, and Chai Wah Wu, Member, IEEE Abstract— Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high- performance, custom circuits. This paper presents a circuit opti- mization tool that automates the tuning task by means of state- of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous tran- sistor and wire tuning, general choices of objective functions and constraints, and recovery from nonworking circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer, and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods, we use a technique called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms and the environment in which they are used and presents extensive circuit optimization results. A circuit with 6900 transistors, 4128 tunable transistors, and 60 independent parameters was optimized in about 108 min of CPU time on an IBM Risc/System 6000, model 590. Index Terms—Adjoints, circuit tuning, nonlinear optimization, simulation, transistor sizing. I. INTRODUCTION,MOTIVATION, AND PREVIOUS WORK A UTOMATING the circuit optimization process is an important step toward rapidly and robustly designing high-performance circuits. Particularly in the use of custom designs, manually sizing schematics for area, delay, and power is an iterative, slow, tedious, and error-prone approach with circuit simulation in the inner loop. The updating of transistor widths from one iteration to the next in this context relies on Manuscript received September 27, 1997; revised May 4, 1998. This paper was recommended by Associate Editor K. Mayaram. A. R. Conn is with the Department of Mathematical Sciences, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: arconn@watson.ibm.com). P. K. Coulman is with IBM Microelectronics Division, Austin, TX 78758 USA (e-mail: coulman@austin.ibm.com). R. A. Haring is with the Microsystems Department, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: ruud@watson.ibm.com). G. L. Morrill is with the IBM Microelectronics Division, Essex Junction, VT 05452 USA (e-mail: s667403@btvlabvm.vnet.ibm.com). C. Visweswariah is with Computer-Aided Design and Verification, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: chandu@watson.ibm.com). C. W. Wu is with the Department of Mathematical Sciences, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: chaiwah@watson.ibm.com). Publisher Item Identifier S 0278-0070(98)09360-9. human intuition. However, the quest for optimal performance and the importance of short time-to-market make automatic circuit tuning increasingly important. In addition, automatic tuning has the benefit of facilitating design adaptation and reuse. Hence an automatic tuning (and retuning) capability is becoming crucial to the productive design of custom circuits. In the case of gradient-based dynamic tuning, function and gradient values are determined by means of a dynamic (time- domain) analysis of the underlying circuit. In the case of static optimization, a static timing analysis is relied upon to analyze new iterates produced during the optimization process. If circuit blocks are modeled by analytic delay equations, these equations can be differentiated symbolically to determine gradients. Unfortunately, this procedure is not applicable to custom designs because of the lack of availability of delay models for arbitrary transistor-level circuits. In any type of circuit tuning, the computation of gradients is often the bottleneck in the optimization procedure. Gradients are generally computed by the direct method [1] or the adjoint method [2]. The direct method can provide the gradients of all of the measurements with respect to a single parameter and thus requires as many simulations of the associated sensitivity circuit as the number of tunable parameters. By contrast, in the adjoint method, the gradients of one measurement with respect to all parameters can be obtained in a single simulation of the adjoint circuit but the simulation must be repeated as many times as the number of measurements. There have been many attempts to automate the transistor- sizing problem. One of the earliest papers to apply gradient- based optimization, albeit to a specific network, was that of Hachtel and Rohrer [3]. A later paper [4] suggested a more general approach that also was intended for gradient- based nonlinear optimization. The latter used adjoint gradient computations and exploited sparse matrix methods. One class of methods [5], [6] is based on static timing analysis [7]. The delay of each cell is available either as a precharacterized analytic function of the transistor sizes or as an Elmore delay approximation. In particular, if the Elmore delay model [8], [9] is used, this overall delay is seen to be a posynomial function (a particular algebraic form, see [10]) of the transistor widths, and geometric programming techniques apply. By a simple mapping of variables, the objective is converted to a convex function [5] and hence any minimum of the latter is guaranteed to be a global minimum. The advantages of static-timing-based methods include ef- ficiency, the ability to handle large designs, and the fact that they do not require input patterns to carry out the tuning. One 0278–0070/98$10.00  1998 IEEE