Ultra-Short Pulse I-V Characterization of the Intrinsic Behavior of High-κ Devices Chadwin D. Young 1 , Yuegang Zhao 2 , Michael Pendley 1 , Byoung Hun Lee 1,3 , Kenneth Matthews 1 , Jang Hoan Sim 1 , Rino Choi 1 , Gennadi Bersuker 1 , and George A. Brown 1 Tel: 512-356-3612, Fax: 512-356-7640, e-mail: chadwin.young@SEMATECH.org 1 International SEMATECH, 3 IBM and Assignee, 2706 Montopolis Dr, Austin, TX, 78741, U.S.A. 2 Keithley Instruments, 30500 Bainbridge Road, Cleveland, Ohio, 44139, U.S.A. 1. Introduction V t instability, mobility degradation, and reliability are key issues in the evaluation of implementing high-κ gate dielectrics. Recent studies on transient charge trapping indicate that these issues are actually closely related to each other. Transient charge trapping of high-κ gate dielectrics and their relaxation are found to be major sources of device instability, and the impact of these phenomena on reliability evaluation has been studied [1-5]. The trap centers can be “charged” and “discharged” relatively fast, and they adversely affect the results of conventional DC approaches (i.e., I d – V g and I d – V d ), which impact mobility [6]. To evaluate the intrinsic nature of the high-κ gate stack, new measurement methodologies that attempt to measure the intrinsic characteristics of high-κ gate dielectric structures in the absence of trapped charge are necessary. In this work, an ultra-short pulse measurement will be utilized to demonstrate the impact of transient charging on DC I d -V g measurements, and it will be shown that a significant portion of mobility degradation observed in high- κ devices is actually due to measurement error originating from transient charge trapping during the DC measurements. 2. Methodology Fast transient (i.e., short pulse) measurement and analysis has been studied to address the need for improved characterization strategies [7, 8]. However, transient charge trapping has been found to affect DC measurements that can occur within the order of µsec [1]. Thus, to investigate the intrinsic properties of high-κ gate stacks with minimal charge trapping, a significantly faster measurement than previously reported is needed. The concept of the high speed pulsed I-V measurement was first introduced and used to study the self-heating effect in SOI MOSFETs [9] where K. Jenkins, et al., demonstrated: 1) the use of a 10nsec pulse to make self-heating negligible, and 2) the pulsed performance of SOI devices is superior to DC characteristics. This method can be adapted to characterize the I d –V d , I d –V g characteristics of high-κ devices with very short pulse durations to minimize or eliminate the effect of fast charge trapping. Fig. 1 shows a diagram of the system configuration where a Keithley Model 4200-SCS provides the DC bias as well as the control of the pulse generator and the digital scope via GPIB. In the pulse I-V ramp measurement, a train of continuous pulses, with duty cycle well below 0.1%, is produced. The drain current is extracted from the amplitude of the response pulse voltage at the drain terminal. Fig. 1 illustrates a screen shot of the input and output pulses from the scope where the output can be converted to I d and plotted versus V g to create the single V DD 4200-SCS DC bias/Control Pulse Generator Scope GPIB Bias Tee Pick-off Tee Trigger V d V g V d Output V g Input V d Output V g Input a) b) V DD 4200-SCS DC bias/Control Pulse Generator Scope GPIB Bias Tee Pick-off Tee Trigger V d V g V d Output V g Input V d Output V g Input a) b) Fig. 1. a) Experimental setup using a MOSFET in an inverter configuration. b) “Screen shot” of the input (V g ) and output (V d ) waveforms for the configuration (t r =t f =2ns, pulse width = ~5 ns) 0.0 0.5 1.0 1.5 2.0 0 100 200 300 400 500 600 700 ISSG SiO 2 Control nFET W/L = 10/0.5µm V d = 100mV 35 ns Pulse, t r = t f = 2ns DC Ramp Drain Current [ µ µ µ µA] Gate Voltage [V] a) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 50 100 150 200 250 300 350 V g = 0.5 V V g = 1.0 V Drain Current [ µ µ µ µA/ µ µ µ µm] Drain Voltage [V] DC Ramp Pulse V g = 1.5 V b) Fig. 2: Benchmark comparison of “ramped” pulse I-V and DC I-V in conventional: a) I d -V g and b) I d -V d characteristics for 2 nm SiO 2 . pulse measurement result in Fig. 3. Multiple pulses can be averaged for optimized resolution. Pulse amplitude degradation along the path of ultra short pulse was calibrated using a MOSFET with a SiO 2 gate dielectric that shows no charge trapping behavior as shown in Fig. 2. Fig. 2 demonstrates an example calibration on a 2 nm in-situ steam generated (ISSG) oxide. For this study, an ~1 nm chemical oxide interfacial layer (IL) with a 3 nm Atomic Layer Deposited (ALD) HfO 2 gate dielectric upon the IL was fabricated using conventional planar CMOS processing with a source/drain activation done at 1000°C for 10 sec. 3. Results and Discussion Transistors with W/L = 10/0.5 µm were subjected to short pulse measurements as outlined in section 3 and [7, 8]. “Single pulse” (SP) I d -V g measurements were done with t r = t f = pulse width (PW). Each SP measurement started and ended at V g ± 1 V as the discharge condition for nMOS and pMOS, respectively, with the top of the pulse taken to achieve a |V g -V t | match in inversion. A difference between the I d -V g curves generated by the up and down swing of V g reflects the effect of the charge trapping (Fig. 3). As illustrated in Fig. 3, charge trapping increased as gate bias increased further into inversion for the nMOS case while pMOS trapping is negligible. The pulsed data superimposed with the nMOS DC I d – V g characteristic demonstrates Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004, - 216 - C-3-3 pp. 216-217