Effects of Optimization of Gate Edge Profile on sub-45nm Metal Gate High-k Dielectric Metal-Oxide-Semiconductor Field Effect Transistors Characteristics C. Y. Kang, R. Choi, S. H. Bae 1 , S. C. Song, M. M. Hussain, C. Young, D. Heh, G. Bersuker and B. H. Lee 2 SEMATECH 2706 Montopolis Drive, Austin, TX 78741, USA, 1. Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78758, 2. IBM Assignee TEL: (512) 356-3527, Fax: (512) 356- 7640, chang.yong.kang@sematech.org ABSTRACT The impact of process integration on device characteristics of metal gate/high-k devices was investigated systematically. It was found that the profile of the gate stack edge and subsequent processes should be optimized to achieve low gate-induced drain leakage (GIDL), gate leakage, and high drive current. For low standby power (LSTP) applications, a protruded high-k dielectric layer was more desirable. With an optimized gate edge profile, we achieved 100X lower off-state current compared to previous reported results. However, the degradation in saturation current was minimal. INTRODUCTION It is well recognized that high-k dielectrics provide a low off-state leakage current, which is extremely useful for low standby power (LSTP) applications. Intrinsically, high-k devices have decreased gate leakage due to their increased physical thickness for the same equivalent oxide thickness (EOT). Also, it has been reported that high-k devices are better for controlling gate-induced drain leakage (GIDL) and reducing I gate than thin SiON devices [1-4]. In integrating conventional SiON with poly-Si gate stack devices, gate re-oxidation is performed to anneal out process-induced defects (PIDs) and to round the gate bottom edge profile to reduce the vertical field [5-6]. This rounded edge suppresses GIDL and improves hot carrier reliability. When integrating a high-k/metal gate stack, however, this gate re-oxidation process is difficult because of the metal electrode oxidation. In addition, it is expected that high-k dielectric yields a higher vertical field due to its higher dielectric constant, which in turn increases GIDL. Therefore, a high-k undercut followed by an oxide gap fill or nitride layer may suppress GIDL. However, the effect of this gate stack structure on off-state leakage current has not yet been systematically studied. EXPERIMENTAL Various thickness combinations of top hafnium oxide (HfO 2 ) and bottom silicon dioxide (SiO 2 ) were prepared using <70 nm TiN gate metal-oxide semiconductor field-effect transistor (MOSFET) fabrication process (Fig. 1). In this flow, HfO 2 films (3 - 5nm) were atomic layer deposited (ALD) on top of a 0.6nm ~1.9nm bottom SiO 2 layer. After gate patterning, the gate dielectric layer in the source/drain (S/D) extension region was removed with a wet or dry etch. The wet and dry etching and cleaning methods were optimized to minimize dielectric damage and to control the gate edge profile (Fig. 2). Then, a thin nitride layer was deposited to protect the gate dielectric films. Lightly doped drain (LDD) and halo were implanted through this thin nitride layer, with an optimized implantation dose and energy process to ensure a proper overlap of LDD and control of short channel behaviors and GIDL. S/D activation and post-metallization annealing were then performed. Equivalent oxide thickness (EOT) ranged from 0.9nm to 2.8nm after device fabrication. For comparison, 2.5nm SiON with a poly-Si device and HfO 2 with a TiSiN gate device were also fabricated. L gate was in 60~80 nm range. Fig. 3 shows typical GIDL characteristics for the thin SiON and HfO 2 (EOT=1.2 nm) devices. For the thin SiON transistor, the dramatic increase of I g led to increased drain-to-gate leakage current. Compared to the SiON device, the high-k device achieved an excellent I off (GIDL) as well as reduced I g . RESULTS AND DISCUSSION Fig. 4 shows how the gate edge profile affects GIDL. A dramatic decrease in GIDL and I g was observed for the more protruded high-k dielectric structure even though linear and saturation current voltage (I- V) characteristics of both devices are almost identical. According to a MEDICI simulation, a laterally recessed or protruded high-k edge structure is more desirable for suppressing GIDL due to the reduced vertical field caused by nitride (i.e., thicker EOT) and the reduced doping concentration caused by the increased LDD implantation buffer layer resulting in reduced gate overlap area, respectively (Fig. 5). However, the experimental results indicate that leakage current increased dramatically as the lateral high-k recess was increased. This discrepancy between the simulation and experimental results is mainly due to the leakage path formation in the heterogeneous interface between the high-k and nitride. Since the maximum vertical electric field (E m,max ) is located in the gate overlap region, GIDL increases for intermediately recessed (0~5 nm) structures (Fig. 6). To clean and etch out the residual metal gate and high-k layer after poly-Si/metal gate stack patterning, wet etch and dry etch techniques were developed. Transmission electron microscopy (TEM) images show that the profiles at the gate edge after gate etch were almost identical for both wet and dry etch (Fig. 7). However, the gate-to-substrate leakage current and the gate-to-drain leakage current increased in the plasma- treated devices, indicating that plasma damage could increase off-state leakage. Using our novel wet etch technique, gate leakage currents were dramatically reduced while other device parameters were almost identical. Dielectric breakdown characteristics are shown in Fig. 8. Inversion Voltage breakdown (V BD ) in the recessed high-k structure decreased. The wider distribution of I gate was due to the leakage path formation in the heterogeneous interface between the high-k and nitride in the gate edge recessed structure (Fig. 9). ∆I dlin under drain avalanche hot carrier (DAHC) and bias instability (BI) stresses is shown in Fig. 10-(a). Under DAHC stress, I d difference between the recessed and the protruded structures was insignificant. The reason was that both devices showed almost identical I sub /I b at DAHC condition, which resulted in the similar degradation behavior (Fig. 10-(b)). In the case of BI stress, the increased I g in the recessed devices led to higher ∆I dlin . Furthermore, this degradation did not fully recovered during relaxation stages (V g =-1.0V), indicating permanent damage was generated. However, the protruded device fully recovered during the relaxation stage, indicating charge trapping and detrapping is the main factor. From our previous experiments, it is expected that the interface degradation would be negligible [7]. In protruded structure, I on can be degraded due to the increased R ext , which is induced by blocking LDD and halo implantation. For the protruded structures, however, the decrease of I on was about 5% (Fig. 11). After careful process and device optimization, 100X lower off-state leakage current with reasonable I on was achieved comparing to previously reported values (Fig. 12). CONCLUSION The impacts of process integration on device characteristics of metal gate/high-k device were investigated systematically. Excellent GIDL controllability was achieved by optimizing the gate edge profile and process. After careful process and device optimization, 100X lower off- state leakage current with reasonable Ion was achieved comparing to previously reported values. Off-state leakage current presented in this work is suitable for 45nm LSTP application and beyond. Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -1112- J-8-3 pp. 1112-1113