Abstract— We report an area-efficient 8bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680nW and the total chip area is 0.035 mm 2 . We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 ± 0.47 dB, 57.90 ± 2.82dB, -53.58 ± 2.15 dB, and 6.65 ± 0.07 bits, respectively. I. INTRODUCTION ECENTLY, multichannel neural interface systems have been implemented to monitor neural activities [1-2]. For the comprehensive analysis of neural activities, it is essential to realize simultaneous real-time monitoring of multiple sites in 3D electrode arrays with 64 channels or more. Typically, neural activities such as spike contain most of information in the bandwidth below 10 kHz with maximum amplitude of ±500 μV [3]. In these microsystems, the neural signals should be amplified and converted into digital signals to be transmitted to wired/wireless communication channels between the implanted system and the external world. Simultaneous access of multiple sites requires better noise immunity in analog-to-digital converters (ADC) in a small form factor at low power. A successive approximation register (SAR) ADC is one of the suitable candidates for neural interface applications due to its simplicity, low power consumption, and reasonable resolution. With a gain of 60 dB prior to the ADC, the quantization noise is required to be less than 5 mV rms which can be achieved by 8 bit or higher resolution capability of ADC. Fig. 1 shows a conventional 8 bit SAR ADC structure which typically consists of three parts: capacitor array (for sample and hold and DAC), comparator, and successive approximation register (SAR). For relatively lower resolution ADCs (<6b), the comparator and SAR consume most power [4]. However, as the resolution of ADCs increases, the power consumption required for charging and discharging the capacitor array becomes significant. Also, the total capacitance required for DAC increases exponentially This work was partly supported by NSF Project #0735481 and partly by NSF Center for Wireless Integrated Microsystems. Sun-Il Chang and Euisik Yoon are with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA (email: schang@umich.edu, esyoon@umich.edu). proportional to the number of bits. In the high resolution ADCs, the capacitor array takes most of the area and power consumption. It becomes more important to reduce the total capacitance and area as the number of bits required in ADC increases and multiple implementations of ADCs is needed. Chang, et al. reported an effective switching method to reduce the power [5]. However, this switching technique can reduce only half of the power in conventional capacitor arrays. Yang, et al. proposed an energy-efficient ADC with a small form factor [6]. However, relatively complex algorithm has to be implemented for practical use in neural microsystems. In this paper, we propose an area-efficient 8 bit SAR ADC using dual capacitor arrays. Using the dual capacitor array banks, we can reduce the required capacitor array area by a factor of 2 N/2-1 compared to the conventional approaches. This feature can not only reduce the area but also the power consumption by eliminating the power required for charging/discharging the capacitor array. II. AREA EFFICIENT SAR ADC ARCHITECTURE A. Dual Capacitor Arrays The key idea of the proposed SAR ADC is to perform the successive approximation in both sides of comparator inputs using dual capacitor arrays rather than only in one side. As A Low-Power Area-Efficient 8 bit SAR ADC Using Dual Capacitor Arrays for Neural Microsystems Sun-Il Chang and Euisik Yoon R Fig. 1: The overall structure of conventional SAR ADC Fig. 2: The overall structure of the proposed area-efficient SAR ADC 1647 31st Annual International Conference of the IEEE EMBS Minneapolis, Minnesota, USA, September 2-6, 2009 978-1-4244-3296-7/09/$25.00 ©2009 IEEE