RESEARCH ARTICLE Low‐power and wide‐band delay‐locked loop with switching delay line Adel Rezaeian 1 | Gholamreza Ardeshir 1 | Mohammad Gholami 2 1 Electrical Engineering, Babol Noshirvani University of Technology, Babol, Iran 2 Engineering and Technology, University of Mazandaran, Babolsar, Iran Correspondence Mohammad Gholami, Engineering and Technology, University of Mazandaran, Babolsar, Iran. Email: m.gholami@umz.ac.ir Summary A low‐power and wide‐band delay‐locked loop (DLL) is presented. Switching the delay line is used to enhance the input frequency range of the DLL. First delay line with short delay times is designed for high frequencies, and second delay line with long delay times is designed for low frequencies. Also, a switching circuit is used to control the delay lines. Proposed delay lines give delay range 0.5 to 34 nanoseconds in which DLL can operate input frequency range of 30 MHz to 2 GHz. This DLL has been simulated in 0.18‐μm CMOS technology. The simulated root‐mean‐square and peak‐to‐peak jitters are 3.12 and 11.03 picoseconds at 2 GHz, respectively. The power dissipation at 2 GHz is 3.24 mW for a supply voltage of 1.8 V. KEYWORDS delay‐locked loop, phase detector, charge pump, delay line, delay cell 1 | INTRODUCTION Delay‐locked loop (DLL) has widely been used in synthesizers, clock/data generation and recovery, 1,2 and transceivers. 3 For a DLL, important parameters are small area, wide frequency range, good stability, low jitter, and low power con- sumption. 4 Figure 1 shows a conventional DLL structure that consists of phase detector, charge pump, loop filter, and voltage‐controlled delay line (VCDL). Phase detector converts the phase difference of input clocks to UP or DOWN signals. Charge pump and loop filter provide the controlled voltage required for delay line. This voltage regulates the delay of delay line so that the VCDL output clock is locked with reference clock. The voltage‐controlled delay line has an important role in frequency range and power consumption for a DLL. 5 Figure 2 shows a delay line with 5 delay cells in which delay of each cell is determined by the controlled voltage. The total delay for this VCDL is: T VCDL ¼ N × T cell (1) where N is the number of delay cells, T cell is the delay of each cell, and T VCDL is the delay for the delay line. The harmonic locking is a common problem in DLLs. For wide‐range DLLs, if 2 × T VCDL, min ≪ T VCDL, max , harmonic locking may happen. That is, mean output clocks of DLL lock in some periods of input clock instead of 1 period. To avoid the harmonic locking problem, the maximum and minimum total delays of a VCDL, respectively, should satisfy the following inequalities 6 : T clk 2 < T VCDL; min < T clk (2) Received: 16 February 2018 Revised: 19 June 2018 Accepted: 19 June 2018 DOI: 10.1002/cta.2539 Int J Circ Theor Appl. 2018;1–13. © 2018 John Wiley & Sons, Ltd. wileyonlinelibrary.com/journal/cta 1