International Journal Of Scientific & Engineering Research, Volume 4, Issue 8, August 2013 ISSN 2229-5518 IJSER © 2013 http://www.ijser.org Design and Analysis of Power and Area Efficient 2/3 Prescaler Using E-TSPC Logic Anish M George PG Scholar, VLSI & Embedded Systems, Saintgits College of Engineering, Kottayam Prof. Riboy Cheriyan ECE Department Saintgits College of Engineering, Kottayam anishm07@yahoo.com Abstract- One of the important functional blocks in frequency synthesizers is the high speed dual modulus prescaler. The bottleneck of the dual modulus prescaler design is that it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) usually consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. In general, a divide-by-N/N+1 counter consist of flip flops and some extra logic implemented using logic gates which determine the terminal count. Here an E-TSPC logic based divide-by-2/3 prescaler suitable for low supply voltage (0.9V) and low power applications is been designed and implemented wherein the counting logic and the mode selection control are implemented using a single transistor. Thus the critical path is reduced which in turn enhances its working frequency. Simulation results show that, compared with the conventional TSPC and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler which incorporates the proposed 2/3 prescaler are designed and implemented. Simulation results show that the power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs. All prescalers were designed using the same 0.18μm TSMC CMOS process technology and simulated using Mentor Graphics ELDO. Index Terms-Extended True Single Phase flip flops (ETSPC FFs), prescaler, low power, and low voltage . ——————————  —————————— 1 INTRODUCTION One of the critical functional blocks in frequency synthesizers is the high speed dual modulus prescaler. It operates at the highest frequencies and consumes more power than any other circuit blocks of the frequency synthesizer. Hence the design of dual modulus prescaler is so crucial. A dual modulus prescaler usually consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. For example the topology of a divide-by-8/9 prescaler is implemented in the work done by Xiao Peng Yu [1] which has one 2/3 prescaler unit and two divide-by-2 units. In general a divide-by-N/N+1 counter (otherwise named as prescaler) consists of flip flops and some extra logic implemented using logic gates which determines the terminal count. Various flip-flop based designs have been proposed to improve the operating speed of dual-modulus prescalers (also called divide-by-N/N+1 counter). Conventional flip flop based N/N+1 counter designs suffer from large load capacitance which limits the maximum operating frequency which in turn increases the power consumption. Therefore, dynamic and sequential circuit techniques [2-4] or clocked logic gates such as, True Single Phase Clocks (TSPC) have to be used to reduce the circuit complexity, power dissipation and increase the operation speed. TSPC logic based designs can be further enhanced by using the Extended True Single Phase Clock (E-TSPC) logic. E-TSPC logic based designs are more suitable for high speed and low power applications. In this logic it removes the transistor stacked structure and thus they are more sustainable for low VDD operations. So here in this paper an E-TSPC logic based divide-by-2/3 prescaler design suitable for low supply voltage and low power consumption applications is been proposed. Here the counting logic and the mode selection control are implemented using a single transistor. So this eventually reduces the critical path and hence the operating frequency also increases. Here the objective is to design and implement an E-TSPC based 2/3 prescaler which uses only a single transistor to implement the counting logic as well as the mode selection control. The power dissipation, delay and area of the proposed prescaler should not be much greater than the conventional prescalers. Also design and implement a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler incorporating the proposed 2/3 prescaler. The power dissipation and the delay of the proposed multimodulus prescalers should also not be much greater than the existing multimodulus prescaler. An idea of different existing prescaler designs which include both TSPC and E-TSPC based designs is given in section 2. Next, the description of our proposed 2/3 prescaler, 32/33 prescaler, 47/48 prescaler and multimodulus 32/33/47/48 prescaler is given in section 3. The comparative results based on our proposed approach