A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-Based 0-1 MASH ADC with Direct Digital Background Nonlinearity Calibration Kareem Ragab and Nan Sun The University of Texas at Austin, Austin, TX 78712 Abstract — A direct digital background calibration technique to correct nonlinearity errors in VCO-based 0-1 MASH ΣΔ ΣΔ ΣΔ ΣΔ ADCs is presented. The proposed technique altogether corrects VCO gain error, nonlinearity, and capacitor mismatch of the residue generating DAC. It improves SNDR of the prototype ADC from 60dB to 73.4dB in 2.5MHz signal bandwidth. The ADC consumes 4.8mW from 1.8V supply in 180nm CMOS. The measured convergence time is only 64ms. Index Terms — Analog-to-digital converters, voltage controlled oscillator, background calibration. I. INTRODUCTION Ring voltage-controlled oscillators (VCOs) provide inherent voltage-to-phase integration and quantization, which makes them ideally suited for noise-shaped ADCs. However, their nonlinearity severely limits performance. In previous works, this limitation was overcome using indirect replica-based background calibration [1]-[3], high- order ΔΣ loop filtering [4]-[5], and using the VCO as the second stage quantizer of a 0-1 MASH [6]-[7]. The mostly digital single stage architecture of [1]-[3] has the advantage of small area. However, it requires high oversampling ratio (OSR) and sampling rate (f s ). Additionally, calibration accuracy is limited by replica- matching. Embedding the VCO in a high-order ΔΣ loop [4]-[5] reduces its linearity requirement and f s . However, their mostly analog nature negates scaling benefits gained by using the VCO. The 0-1 MASH architecture [6]-[7] relaxes the requirement on VCO linearity and f s in proportion to the first stage coarse quantizer resolution and it mostly consumes dynamic power. However, residue generating DAC element mismatch and VCO linear gain drift introduce additional errors, in the form of missing codes (gaps) in the ADC transfer function at the coarse quantizer decision boundaries. These errors were mitigated using DEM and background VCO linear gain estimation [6], foreground calibration [7], or suppressed by embedding the 0-1 MASH in a high-order ΔΣ loop [5]. This paper presents a background calibration technique that simultaneously corrects for DAC mismatches, interstage gain error, and VCO nonlinearity. In contrast to [6], the technique does not need analog dither and requires minimal change to the basic 0-1 MASH architecture. To our best knowledge, the proposed technique is the first to demonstrate direct background VCO nonlinearity calibration with a short convergence time. Measured convergence time of only 64ms is comparable to those of [1]-[3] where indirect calibration schemes were adopted. In those schemes, the absence of the input signal from the replica path enables short convergence time. However, this sacrifices calibration accuracy as the schemes of [1]-[3] rely on accurate replica-matching, which is hard to guarantee under process, voltage, and temperature (PVT) variations. A direct application of the technique in [1] to calibrate the VCOs in the signal path suffers from very long convergence time, in the order of tens of seconds [1]. Our proposed technique achieves fast convergence while directly calibrating the main VCOs resulting in accurate and robust operation. Fast convergence speed is achieved by reducing estimation error in the calibration loop. This is enabled by the use of narrow detection windows centered on the coarse quantizer decision boundaries. Only ADC outputs corresponding to input samples falling inside these detection windows, referred to as calibration samples, are used by the calibration unit to estimate the correction parameters. This reduces the variance of the calibration samples [8] which significantly shortens startup convergence time and increases calibration loop tracking bandwidth. II. ADC ARCHITECTURE Fig. 1 presents the proposed ADC architecture and timing diagram. The ADC operates in three phases, with 0.25T s allocated for input tracking, 0.25T s for coarse quantization and residue settling, and 0.5T s for fine quantization; where T s is the conversion cycle. This is realized using one 25% duty-cycle clock   and two non-overlapped 50% duty- cycle clocks   and   . The input is first bottom-plate sampled on a differential thermometer capacitive DAC (CDAC) at the end of the input tracking phase. A 14-level main flash, along with an auxiliary flash, is then triggered to perform coarse quantization. Coarse quantization result (D c ) is taken as either the main or the auxiliary flash output based on a pseudo-random (PN)-sequence, and is subtracted from the input using CDAC to generate the residue which settles by the end of the second phase. Discrepancy between corresponding comparators’ outputs in main and auxiliary flash is detected using XOR gates. The 14 generated flags {f -7 , f -6 , …, f +6 , f +7 } are used by the calibration unit to capture ADC output samples used to estimate decision boundary gaps in the ADC transfer function as further explained in the next section. 978-1-4799-8682-8/15/$31.00 ©2015 IEEE