Scan Paths through Functional Logic Chih-chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, and Mike Tien-Chien Lee* Electrical and Computer Engineering Univ. of California Santa Barbara, CA 93106 ABSTRACT Conventional scan design imposes considerable area and delay overhead due to the use of larger flip-flops and addi- tional connections between flip-flops. We propose a low- overhead scan design methodology which exploits the pos- sibility of utilizing input vectors and the test-mode point insertion technique to establish scan paths through the combinational logic. The technique re-uses the existing functional logic; as a result, the DFT overhead can be reduced. I. INTRODUCTION Automatic test pattern generation (ATPG) for sequen- tial circuits is a difficult problem [l, 21 because of the lack of direct controllability of the present state lines and direct observability of the next state lines. Design- for-Testability (DFT) techniques aiming at improving controllability and observability of the state lines have been proposed, such as full scan [3, 41 and partial scan [5, 6, 7, 8, 93. However, the area and delay overheads imposed by conventional scan can be significant, due to the extra scan multiplexers (MUXs) in the scan flip-flop (assuming the MUXed D flip-flops are used) and routing area for the scan chains. To alleviate the above DFT penalty, we proposed low- overhead scan design methods which exploit the control- lability of primary inputs and test-mode point insertion technique to establish scan paths through the existing combinational logic. A scan path is defined as a physical path between two flip-flops that can be fully sensitized in the test mode. The scan design methodoiogy called, free-scan [lo], is based on an observation that by set- ting appropriate values at primary inputs during the test mode, some combinational paths between flip-flops can be sensitized and thus a portion of the scan chain can be established without any DFT overhead. In [ll] we pro- posed a test-mode point insertion technique which further extends the free-scan technique and utilizes more existing combinational logic for establishing the scan paths. In this paper, we study the relation of finite state machine (FSM) encodings with the free-scan design and show an algorithm which integrates the free-scan and test-mode point insertion methods together. Our essential ideas of designing scan paths through combinational logic can be illustrated in Figure 1 and Figure 2. In Figure 1, a scan path from F2 to F1 is formed through the combinational logic (indicated by the dashed line) by assigning 0 and 1 at the inputs xl and z2, respectively. Since F1 costs no scan overhead for the scan order from F2 to F1, F1 is called a free-scan flip- flop. Figure 2 shows an example of a test-mode point insertion. The test-mode points are established by ap- Fujitsu Laboratories of America* 3350 Scott Blvd., Bldg #34 Santa Clara, CA. 95054 Fig. 1. Example of a sequential circuit. A free-scan path (in dashed line) is established from F2 to F1 by (~1~2) = 01. F Fig. 2. Example of a test-mode point insertion. propriately inserting two-input AND or OR gates with a common test-mode input. Figure 2(a) shows a portion of a sequential circuit. By inserting a test-mode point at the output of F4 and setting the primary input x to 0 during the test mode, a scan chain F1 --+ F2 --+ F3 can be formed through the combinational logic, as shown in the dotted line of Figure 2(b). In the following, we review some related previous works. The works in [12, 1.31 presented algorithms to reduce scan overhead by attempting to merge scan MUXs into the combinational logic during logic synthesis. In [13], the concept of test synthesis constraints was proposed, where a mechanism was used to describe the conditions which must be met by the synthesized circuit in order to be fully testable. The concept of embedded scan was also proposed where attempts were made to embed the multi- plexers for scan into the logic immediately preceding the scan flip-flops. A technique of testpoint insertion to im- prove the sequential ATPG fault coverage was proposed in [14]. This technique is different from the scan method. The idea was to insert a set of test-cells into a circuit to improve the observability and controllability of some in- ternal signals. The size of a test-cell could be large and the compound effect of adding such cells may result in significant area overhead (a t,est-cell requires at least one flip-flop and two multiplexers). On the other hand, the test-mode point used in [ll] is simply a two-input AND or a two-input OR gate and the purpose of inserting test- mode points is to establish scan paths by utilizing existing logic, which in turn makes scanned flip-flops fully observ- able and controllable. 11. FREE-SCAN DESIGN To utilize the concept of free-scan, we have to analyze the entire circuit to determine all the free-scan flip-flops and the associated input assignments, and then select the best input assignment to maximize the number of free- scan flip-flops for constructing the scan chain. In the fol- lowing, we assume a sequential circuit has primary inputs 22,62, -i 487 IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-3177-6 $5.00 0 1996 IEEE