A Compact Charge-Based 4-Bit Flash ADC Circuit Architecture for ANN Applications A. Schmid, Y. Leblebici and D. Mlynek Abstract : A charge-based flash analog digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4-bit $'& KDV EHHQ UHDOL]HG ZLWK  P GRXEOHSRO\ SURFHVV DQG tested, confirming its linearity over the full range and a conversion speed of 10 Msamples / s. Introduction : The requirements of A/D conversion in mixed analog-digital ANN architectures may impose unique specifications on ADC circuit performance which are quite different from classical ADC performance requirements. The silicon area occupied by the ADC should be minimized, since a large number of such units are typically needed in ANN architectures. The sampling speed should be as high as possible, in order to accommodate fast-changing input signals such as those encountered in real-time image processing and pattern recognition. The required accuracy (resolution), on the other hand, may be lower than that used in most of classical ADC applications, since the inherently error-tolerant properties of ANN operation typically compensates for the lower resolution of the processed signal. Here, we present a very compact flash ADC circuit architecture which is based on the charge-based Capacitive Threshold Logic (CTL) circuit concept introduced earlier [1]. The circuit is CMOS-compatible, operates on a simple two- phase non-overlapping clock scheme, and it requires no externally generated reference voltage levels other than VDD and GND for its operation. Circuit description : The circuit diagram of a 4-bit CTL- based ADC is given in Fig. 1. The converter essentially consists of four threshold logic gates, i.e., four capacitive rows, which accommodate analog and digital input signals. The capacitive threshold logic gates are actually connected in a cascade configuration; the gate that generates the most significant bit (MSB) output is directly driven by the analog input signal, whereas the gates that generate the lesser significant bits are driven by the analog input as well as by the higher-order digital output signals. At the functional level, the operation of the four CTL gates can be described as follows: VOUT3 = VDD if VA > (8/16) VDD (1) VOUT2 = VDD if VA > (12/16) VDD – (8/16) OUT3 V VOUT1 = VDD if VA > (14/16) VDD – (8/16) OUT3 V – (4/16) OUT2 V VOUT0 = VDD if VA > (15/16) VDD – (8/16) OUT3 V – (4/16) OUT2 V – (2/16) OUT1 V Note that the four output bits (VOUT0 through VOUT3) are generated by four “threshold decisions”, each of which is performed by a mixed-input CTL gate. The inherently recursive nature of the decision process described in (1) implies that the LSB-delay is proportional to the number of bits in the output word, and that the higher-order outputs create a ripple effect for the lower-order bits. Yet, the entire conversion operation given in (1) can be completed in a single clock cycle. As opposed to earlier, similar charge-based ADC architectures [2], [3], this circuit does not require a subsequent decoder circuitry to convert a “thermometer code” output of voltage comparators into conventional binary output. OUT3 OUT2 OUT1 OUT0 V A 2 4 4 8 8 8 15 14 16 16 16 12 8 16 V DD φ E φ R φ R Figure 1 : Simplified circuit schematic of the 4-bit ADC circuit. In the following, we examine the operation of a single mixed-input CTL gate, which comprises the basic building block of the four stage capacitive ADC structure shown in Fig. 1. Note that each CTL gate consists of a row of weighting capacitors, and a chain of inverters which functions as a voltage comparator (see Fig. 2). COMPARATOR row OUT V th1 THRESHOLD COLUMN C T φ E φ E φ R V A C A ANALOG INPUT COLUMN ... ... φ E φ E φ R V i C i DIGITAL INPUTS COLUMNS φ E φ R φ R evaluation reset φ R φ E Figure 2 : Circuit description of a mixed-input CTL gate. Here, CA denotes the weight capacitor of the analog input V A , Ci denote the weight capacitors of the digital inputs, and CT denotes the threshold capacitor (note that all of these capacitors are realized as integer multiples of a unit capacitor). The mixed-input CTL gate operates with a two-phase non- overlapping clock scheme consisting of a reset (precharge) phase (φR) and an evaluation phase (φE). During the reset phase, the total charge accumulated in the capacitive row is given by: Qrow(reset)=Vth1CA+(Vth1–VDD)CT+Vth1 ∑ = m 1 i Ci (2) where Vth1 is the logic threshold voltage of the first inverter within the voltage comparator. During the evaluation phase, all inputs (analog and digital) are applied to the bottom plates of the respective capacitors, while the threshold capacitors are connected to ground. The amount of total charge in the capacitive row is now given by: Qrow(eval)=(Vrow–VA)CA+(Vrow –0)CT+ ∑ = m 1 i (Vrow–Vi)Ci (3) Since the total row charge during the reset phase must be equal to the row charge during the evaluation phase (due to charge conservation), the row voltage must exhibit a certain