Analog Integrated Circuits and Signal Processing, 28, 115–121, 2001 C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Statistical Design of the Four-MOSFET Structure TUNA B. TARIM 1 AND MOHAMMED ISMAIL 2 1 Texas Instruments, Inc., 12500 TI Boulevard, Dallas, Texas, 75243, USA 2 Analog VLSI Lab, Department of Electrical Engineering, Ohio State University, Columbus, Ohio, USA E-mail: tuna@ti.com; ismail@ee.eng.ohio-state.edu Received June 27, 2000; Revised September 21, 2000; Accepted December 1, 2000 Abstract. The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 µm process using MOS transistor Level-3 model parameters. Experimental results are included in the paper. Key Words: analog MOS ICs, yield enhancement, statistical design, four-MOSFET structure, VLSI I. Introduction The need for the robust design of low voltage low power CMOS analog VLSI circuits is tremendously growing. The major driving force for this growth is the need for single-chip solution for systems with combined analog and digital circuitry, also known as system on a chip (SoC). Many emerging applications which require re- duced supply voltage and low power consumption are based on analog/digital mixed mode signal processing VLSIs. Fully integrated continuous time circuits can be re- alized in MOS technology by using MOS transistors operating in the triode region. MOS transistors used in filter applications for implementing linear resistors suffer from nonidealities causing signal distortion due to body effect, mobility variation, device mismatch, etc. Extensive research has been conducted on the fully balanced integrator with MOS resistors. It was demon- strated, using a strong inversion MOS model, that a four-MOSFET structure fully suppresses the even and odd-order nonlinearity terms [1–3]. However, recent works question the widely accepted superiority of the four-MOSFET structure. The result of the discussion is important because the supposed linearity properties of the four-MOSFET structure serves to justify its use in several recent applications [4,5]. For exact cancelation of nonlinearities, exact tran- sistor matching is needed. This, however, is not realis- tic due to random variations [6]. Most of the previous four-MOSFET structure works have not considered random variations; hence, it is important to quantita- tively determine the effect of mismatches on nonlin- earity cancelation. As an application of the four-MOSFET structure, a CMOS down-conversion mixer was introduced in [7]. Matching of the transistors is very important in this ap- plication; mismatch between the input transistors result in K and V T mismatches, and both result in the appear- ance of residual DC offset voltages. A recent work is analyzes the DC offset voltage of this circuit [8] and proposes two approaches to remove DC offset in the circuit. This also underlines the importance of statisti- cally examining the circuit. The four-MOSFET circuit description is given in Section II of this paper. The nonlinearity measurement is described in Section III. Statistical design and results are discussed in Section IV. Experimental results for the statistical design of the four-MOSFET structure is given in Section V. Section VI concludes the work. II. Circuit Description The four-MOSFET structure is illustrated in Fig. 1. All transistors in the circuit are operating in the triode region. The output voltages V o1 and V o2 must