International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 NATIONAL CONFERENCE on Developments, Advances & Trends in Engineering Sciences (NCDATES- 09 th & 10 th January 2015) CMR Engineering College 8|P a g e Low-Complexity Design of FIR Filter Implementation 1 R.VENKATESH , 2 SANTHOSH KUMAR 1 Department of Electronics and Communication Engineering CMR Engineering College, Hyderabad. Venkateshrapolu2008@gmail.com 2 Department of Electronics and Communication Engineering AVANTHI Engineering college, HYDERABAD. Santhosh_gangi@yahoo.com Abstract— this paper presents a programmable digital finite impulse response (FIR) filter for low-power applications. A 10- tap programmable FIR filter was implemented and fabricated in CMOS 0.25- m technology based on the proposed architectural and circuit-level techniques. The chip‟s core contains approximately 130 K transistors and occupies 9.93 mm2 areas. The architecture is based on a computation sharing multiplier (CSHM) which specifically add and shift operation. Efficient circuit-level techniques, namely a new carry-select adder using fast all one finding logic used to improve and 16 percent shorter delay than the original dual ripple-carry carry-select adder. And conditional capture flip-flop (CCFF), are also used to further improve power and performance. Index Terms—Dual transition skewed logic, programmable finite impulse response (FIR) filter. I. INTRODUCTION One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. The FIR filter performs the weighted summations of input sequences and is widely used in video convolution functions, signal preconditioning, and various communication applications. Recently, due to the high-performance requirement and increasing complexity of DSP and multimedia communication applications, FIR filters with large filter taps are required to operate with high sampling rate, which makes the filtering operation very computationally intensive. In the proposed FIR filter architecture, the Computation sharing multiplier (CSHM) [1] is efficiently used for the low-complexity design of the FIR filter. Canonical-signed-digit [2] and signed-power-of- two [3] coefficient representations are widely used in the parallel implementation of FIR filters. Using those Techniques, the FIR filtering operation can be simplified to add and shift operations. Common sub expressions elimination [4], [5] and differential coefficients method [6], [7] also explore low- complexity design of FIR filters by minimizing the number of additions in filtering operations. The main idea of CSHM is to represent the multiplications in the FIR Fig. 1. Transposed direct form (TDF) FIR filter. Adders are critical components of the ALU‟s (Arithmetic Logic Unit) or DSP (Digital Signal Processing) chips [10]. Among various adders, the carry-select adder (CSA) is intermediate regarding speed and area and widely used in mobile applications [11]. CSAs with very large sizes can be constructed hierarchically by combining smaller „block‟ adders [12]. Fig. 5 shows the conventional CSA which consists of two ripple carry adders (RCAs) in each block (except block1), one for Cin (from lower block) = 0 and the other for Cin (from lower block) =1. Instead of using dual RCAs, Chang proposed a 29.2% reduced area CSA with 5.9% speed penalty by replacing one RCA to an add-one circuit [13]. Flip-flops are also crucial elements from both a delay and power standpoint. Conditional capture flip- flop (CCFF) [14] is explained and used in our filter design. CCFF is a dynamic style flip-flop that has a negative setup time and small clock-to-output delay. Moreover, depending on data switching activity, CCFF also reduces the power consumption. Filtering operations as a combination of add and shift operations over the common computation results. The common computations are identified and those are shared without additional memory area. This sharing property enables the computation sharing multiplier approach that achieves high performance and low power in FIR filter implementation. RESEARCH ARTICLE OPEN ACCESS