Multi-Dimensional LUT-based Digital Predistorter for Concurrent Dual-Band Envelope Tracking Power Amplifier Linearization Quynh Anh Pham ∗ , David L´ opez-Bueno #∗ , Teng Wang ∗ , Gabriel Montoro ∗ and Pere L. Gilabert ∗ ∗ Dept. Signal Theory and Comm., Universitat Polit` ecnica de Catalunya (UPC), Castelldefels, Spain # Centre Tecnol` ogic de Telecomunicacions de Catalunya (CTTC), Castelldefels, Spain Abstract— This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory poly- nomial (3D-DMP) behavioral model used in Digital Predistor- tion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3D- Distributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels. Index Terms— Envelope tracking, digital predistortion, lookup tables, power amplifier. I. I NTRODUCTION In concurrent dual-band (DB) transmissions with en- velope tracking (ET) power amplifiers (PAs), several lin- earization challenges have to be addressed. For example, assuming that the nonlinear distortions of concern are those that arise close to the band of interest, it is pos- sible to design specific DPD linearizers for each band, taking into account possible cross-band intermodulation distortion between bands. Moreover, since the envelope modulators efficiency is kept along a limited bandwidth, we cannot supply the power required by the transistor at the same speed of the DB signal’s envelope. Consequently, as explained in [1], we can use a slower version of the instantaneous DB envelope to supply the PA (e.g., sum of the modulus of both baseband signals). Therefore, in concurrent DB ET PAs, specific DPD linearizers are designed for each band to compensate for the in-band and cross-band intermodulation distortion as well as for the slow-envelope dependent distortion that appears when supplying the PA with a slower version of the DB envelope. In this paper we propose a multi-LUT architecture targeting a FPGA implementation of the 3-D distributed memory polynomial (3D-DMP) DPD proposed by the authors in [1]. The proposed 3-D distributed memory LUT (3D-DML) architecture follows the linear/bilinear interpolation and extrapolation presented by Molina et al. in [2]. In addition, a modified version of the Orthogonal Matching Pursuit (OMP) algorithm [3] is proposed to properly select the most relevant LUTs of the 3D-DML model. Experimental results to validate the 3D-DML DPD were obtained using the remoteUPCLab test bed, built by the authors to organize the IMS2017 DPD student design competition [4]. The remainder of this paper is organized as follows. Section II presents the 3D-DML model. Section III de- scribes the proposed best LUTs selection method in details. Section IV demonstrates the measurement results of the proposed selection method on 3D-DML model. Section V gives the conclusions. II. 3D-DML DIGITAL PREDISTORTER To derive the 3D-DMP DPD in [1] into a set of LUTs for FPGA implementation, we have considered the LUT linear/bilinear interpolation and extrapolation presented in [2]. In a concurrent DB transmission, each band will be predistorted by its particular DPD. The input-output relationship in the 3D-DML DPD for Band 1 is defined as x 1 [n]= N1−1 ∑ i=0 u 1 [n − τ u1 i ]f Φ1,i    u 1 [n − τ u1 i ]    + N2−1 ∑ i=1 M2−1 ∑ j=1 u 1 [n]f Φ1,i,j    u 1 [n − τ u1 i ]   ,   u 2 [n − τ u2 j ]    + N3−1 ∑ i=1 K3−1 ∑ k=1 u 1 [n]f Φ 1,i,k    u 1 [n − τ u1 i ]   ,E[n − τ e k ]  (1) where N 1 , N 2 and N 3 are the numbers of delays of the input signal at each branch; M 2 is the number of delays of the interference signal u 2 [n]; K 3 is the number of delays of the supply envelope E[n]; τ u1 , τ u2 and τ e (with τ u1,u2,e ∈ Z and τ u1,u2,e 0 =0) are the most significant sparse delays of the input (u 1 [n]), interference signal (u 2 [n]) and envelope (E[n]); f Φ (u) and f Φ (u, v) are 1-D LUT and 2-D LUT respectively, presented in [2] and further described later in this section. The DPD for Band 2 can be similarly modeled as in (2) with u 2 [n] and u 1 [n] are the input and interfering signals. On the one hand, the 1-D LUT in (1) is a piecewise linear complex function, defined in (2) as the linear com- PREPRESS PROOF FILE CAUSAL PRODUCTIONS 1