UNCORRECTED PROOF 2 Analytical modeling of codes with arbitrary 3 data-dependent conditional structures q 4 D. Andrade, B.B. Fraguela * , R. Doallo 5 Universidade da Corun˜a, Depto. de Electro´ nica e Sistemas, Facultade de Informa´ tica, Campus de Elvin˜a s/n, 15071 A Corun˜a, Spain Received 20 May 2004; received in revised form 28 January 2005; accepted 24 April 2005 8 Abstract 9 Several analytical models that predict the memory hierarchy behavior of codes with regular access patterns have been 10 developed. These models help understand this behavior and they can be used successfully to guide compilers in the appli- 11 cation of locality-related optimizations requiring small computing times. Still, these models suffer from many limitations. 12 The most important of them is their restricted scope of applicability, since real codes exhibit many access patterns they 13 cannot model. The most common source of such kind of accesses is the presence of irregular access patterns because of 14 the presence of either data-dependent conditionals or indirections in the code. This paper extends the probabilistic miss 15 equations (PME) model to be able to cope with codes that include data-dependent conditional structures too. This 16 approach is systematic enough to enable the automatic implementation of the extended model in a compiler framework. 17 Validations show a good degree of accuracy in the predictions despite the irregularity of the access patterns. This opens the 18 possibility of using our model to guide compiler optimizations for this kind of codes. 19 Ó 2005 Elsevier B.V. All rights reserved. 20 Keywords: Memory hierarchy; Cache behavior; Performance prediction; Irregular access patterns 21 22 1. Introduction 23 There has been a growing interest in the study 24 and understanding of the behavior of the memory 25 hierarchies in the past years. The reason is the essen- 26 tial role they play in the performance of modern 27 computers, mainly because of the increasing differ- 28 ence between main memory and processor speeds. 29 One of the most effective ways to reduce the impact 30 of this difference is the usage of memory hierarchies 31 with one or, more typically, several level of caches. 32 The first approach to study the behavior of these 33 systems was the usage of trace-driven simulations 34 [1]. This approach, while very accurate, has many 35 drawbacks: difficulty to store the traces, large com- 36 puting times, and lack of an explanation for the 37 behavior observed in many cases. The first two 38 problems can be overcome by the usage of hardware 39 counters [2], but they still offer no explanations 40 about the behavior observed and they are restricted 1383-7621/$ - see front matter Ó 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.sysarc.2005.04.004 q This work was supported in part by the Ministry of Education and Science of Spain under contracts TIC2001-3694-C02-02 and TIN2004-07797-C02-02, and by the Xunta de Galicia under contract PGIDIT03TIC10502PR. * Corresponding author. Tel.: +34 981 167000x1219; fax: +34 981 167160. E-mail addresses: dcanosa@udc.es (D. Andrade), basi- lio@udc.es (B.B. Fraguela), doallo@udc.es (R. Doallo). Journal of Systems Architecture xxx (2005) xxx–xxx www.elsevier.com/locate/sysarc SYSARC 639 No. of Pages 17, Model 3+ 26 October 2005 Disk Used ARTICLE IN PRESS