Research Article Optimization of CNFET Parameters for High Performance Digital Circuits Shimaa Ibrahim Sayed, Mostafa Mamdouh Abutaleb, and Zaki Bassuoni Nossair Electronics, Communication, and Computer Engineering, Helwan University, Helwan, Egypt Correspondence should be addressed to Shimaa Ibrahim Sayed; shimaa.ibrahim88@yahoo.com Received 11 March 2016; Accepted 14 July 2016 Academic Editor: Anna Richelli Copyright © 2016 Shimaa Ibrahim Sayed et al. is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. e Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. e CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. is paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. erefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits. 1. Introduction CMOS technology faces significant challenges at the nanoscale due to several factors like short-channel effects, a lack of control over static leakage current and source-to- drain tunneling [1, 2]. Now in order to sustain Moore’s Law, it is necessary to look for alternatives like Carbon Nanotube Field Effect Transistors (CNFETs) that have received a lot of attention in the past few years as a promising extension to silicon CMOS for future digital logic integrated circuits. CNFETs show desirable characteristics such as high mobility of electrons movement near ballistic transport and the ability to carry large current and smaller device footprint as compared to conventional Si-MOSFETs [3]. Carbon nanotubes (CNTs) are a promising material for flexible electronics which offer a wide variety of applications such as flexible solar cells, skin-like pressure sensors, and conformable RFID tags [4]. CNFET has many applications in digital circuits such as arithmetic circuits, Full Adder-Subtractor [5–7], and 6T SRAM [8] and there is hybridization between MOS and CNFET to improve performance for digital [9] or analog design [10]. Efforts have been made in recent years on mod- eling and simulating CNT related devices such as CNFET [11, 12] to evaluate the potential performance at the device level. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances and thus improve the speed of CNT ICs [13]. ere has been a previous work which investigates optimum design parameters to propose the suitability of pure and hybrid CMOS-CNFET in a wide range of high performance analog circuits [14]. In this paper, we discuss the design parameters of the CNFETs and show how to optimize these parameters for obtaining high performance CNFET for digital circuit implementation. e optimization is per- formed using HSPICE for extensive simulations. e results obtained are useful for understanding the design parameters of near ballistic CNFETs and for identifying important issues to further improve CNFET performance. is paper is organized as follows: the structure and basic characteristics for CNFETs are discussed in Section 2. Section 3 describes the effect of all design parameters on Hindawi Publishing Corporation Advances in Materials Science and Engineering Volume 2016, Article ID 6303725, 9 pages http://dx.doi.org/10.1155/2016/6303725