FlexTrate A Biocompatible Flexible Electronics Platform for High Performance Applications using Fan-Out Wafer-level Packaging Amir Hanna, Arsalan Alam, Goutham Ezhilarasu, Takafumi Fukushima & Subramanian S. Iyer* Henry Samueli School of Engineering, Electical and Computer Engineering Department University of California Los Angeles, Center for Heterogeneous Integration and Performance Scaling (CHIPS) Los Angeles, CA 90095 s.s.iyer@ucla.edu Abstract—A novel mechanically flexible platform based on fan-out wafer-level packaging (FOWLP) is demonstrated. FlexTrate enables heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package. We demonstrate two applications: 1) a foldable seven segment display that is bendable to 1 mm radius for more than 1000 cycles, and 2) a near field wireless implantable optogenetic system that is bendable to 5mm bending radius. I. INTRODUCTION Commercially available wearable applications typically rely on integration of packaged chips mounted on rigid-flex printed circuit board (PCB) that are partially bendable[1]. The other approach for achieving higher flexibility needed for wearable electronics is the Flexible Hybrid Electronics (FHE) approach, which relies on integration of ultra-thin Si dies (< 50 µm thicknesses) on a flexible organic substrate using printed interconnects to achieve higher flexibility compared to flex-rigid PCBs, as shown schematically in Fig. 1 (a)[2]. However, this approach has three major limitations. Firstly, it is dependent on achieving high yield after: i) wafer thinning and die singulation from bulk inorganic substrates and ii) die handling of potentially warped ultra-thin dies during flip chip bonding [3]. Secondly, conventional FHE does not support high number of I/Os needed for high performance logic and memory dies due to coarse interconnect pitch of printed nanoparticle based conductors [4]. Thirdly, as thinned dies are bent to smaller bending radii, the mechanical bending induced strain can lead in performance degradation of high performance CMOS dies [5]. This is why our approach of integrating FHE relies on embedding mechanically rigid dies in a soft elastomeric molding compound and interconnecting them using Fan-Out Wafer-Level Packaging (FOWLP), which is illustrated schematically in Fig. 1(b). We call this FOWLP based platform: FlexTrate. The bendability of FlexTrate package is similar to the way a bicycle chain bends, which consists of both hard and soft segments that allow for bending. We use soft Polydimethylsiloxanes (PDMS) as the molding compound, which has sufficient flexibility to allow for use of rigid small sized (1-5 mm 2 ) “dielets” without compromising the flexibility of the overall system or inducing stress in the integrated Si dielets even when bent to small bending radii [6]. FlexTrate approach also allows for scaled fine pitch interconnects (<40 μm) using a wafer-level electroplating process, which can allow for on-chip like communication between neighboring dielets as the interconnect pitch approaches that of the back end of the line (BEOL) fat wire level. To sum up, in the flexibility of overall package can be optimized as a function of dielet size, inter-dielet spacing. An important implication of this approach is that FlexTrate allows for heterogeneous integration of high-performance dies, using a high performance electroplated Cu interconnect system similar to that used in rigid FOWLP used extensively in smart portable devices and allows us to pack significant processing power in truly flexible, low form factor, biocompatible, and implantable packages. Fig. 1. (a) Schematic of a single large thin die bonded on flexible substrate in conventional FHE approach, where the die undergoes high stress upon bending to small bending radius (2 mm), (b) schematic of “dielet” approach in FlexTrate, showing multiple Si dielets connected at fine interconnect pitch. II. PROCESS FLOW Fig. 2 shows the schematic of the FlexTrate process integration scheme. FlexTrate follows the die-first Fan-out Wafer-level Packaging scheme practiced for rigid electronics with a few important differences: Fig. 2. Schematic of the FlexTrate Process 250 DISTRIBUTION STATEMENT A. Approved for public release: distribution is unlimited.