1 of 4 Characterization of a CMOS Current-Steering DAC using State-Space Models K. Ola Andersson and J. Jacob Wikner Dept. of E.E., Linköping University SE-581 83 Linköping, Sweden MERC, Ericsson Microelectronics AB Box 1885, SE-581 17 Linköping, Sweden Abstract - Performance limitations on current-steering dig- ital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, match- ing, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic non- idealities. Simulation results are presented and compared to measurement results. The model can be used for fast perform- ance estimation of D/A converters. I. INTRODUCTION For high speed and high resolution communication appli- cations the current-steering digital-to-analog converter (DAC) is suitable [1]. In this work we focus on the dynamic properties of the current-steering converter. With increasing signal frequency, dynamic errors, e.g., nonlinear settling errors and glitches, tend to determine the performance of the DAC. We need good behavioral-level models of the dynamic properties in order to understand the DAC design criteria. In Sec. II we introduce the different nonideal components used in a current-steering DAC. These components are put together to a circuit level model of the whole DAC, as pre- sented in Sec. III. In Sec. IV we present a mathematical analysis of the cir- cuit-level model. The differential equations of the system are given on a state-space form, yielding short simulation times. The model helps us understand what can be done to minimize the influence of dynamic errors. The model is Spice-like, but used in Matlab it has an improved modularity and flexibility. In Sec. V we discuss the application of the model on a 14-bit current-steering DAC. Single-tone and multi-tone properties are discussed. II. NONIDEAL CURRENT -STEERING DAC CIRCUIT ELEMENTS In this work we focus on the influence of unwanted resis- tive and capacitive parts (parasitics). The parasitics in the current sources have one of the most crucial impacts on per- formance. Matching is not considered but can easily be introduced in simulations of the model presented by simply changing the numerical values of currents and parasitics. A. The Current Source The ideal current source (Fig. 1(a)) should have an infi- nite output impedance. A cascoded PMOS implementation of a current source is shown in Fig. 1(b). The cascode tran- sistor increases the output impedance [2], but still the source will have a finite output impedance (Fig. 1(c)). The output impedance contains a capacitive part [1], which will degrade the performance at higher signal frequencies. B. The Switch Using differential signal paths is an effective way of rejecting noise and distortion, e.g., substrate noise or chan- nel charge injection, if the two paths are symmetrically designed [2]. Therefore, differential current switches are commonly used and they are implemented with two or more MOS transistors in parallel (Fig. 2(a)). In this work the switch is represented by the MOS switch-on resistance(Fig. 2(b)). There also exist parasitic capacitances in the switch, but these are lumped into the parasitics of the current source and output wire. C. The Output Wire The output wires of the DAC should have zero imped- ance to reduce the voltage drops. In reality, the wires contain resistive as well as capacitive and inductive parts. For high accuracy, a transmission line model or an RC-ladder should be used for the wire [3]. However, we want to achieve short simulation times, i.e., a small number of circuit nodes. Therefore, we trade accuracy for a lower complexity model. As a simple approximation, we use a resistor and capacitor in parallel, i.e., a simple RC-ladder, as shown in Fig. 3. The impedance includes the internal wire impedance as well as the off-chip load. III. CIRCUIT -LEVEL MODELING In this section we briefly present the ideal current-steer- ing DAC, followed by a presentation of the nonideal DAC constructed with the components described in Sec. II. Fig. 1. (a) Ideal, (b) PMOS, and (c) simplified model of MOS current source.         (a) (b) (c)