– 1 – Influence of Circuit Imperfections on the Performance of DACs J Jacob Wikner 1) , and Nianxiong Tan 2) Abstract Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the perfor- mance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modelled. The purpose of this model- ling is to provide an insightful design guide for high dynamic performance CMOS digital-to-ana- log converters. I. INTRODUCTION Analog-to-digital converters (ADCs) as well as digital-to-analog converters (DACs) are two of the most important building blocks in telecommunication applications. In wideband radio [1] and high speed internet access systems [2], the use of high-speed DACs is required. It is important to send and receive information with as high data-rate and high accuracy as possible. This requires a wide frequency band and high resolution of the transmitting and receiving circuits. To design a DAC meeting these requirements, the static performance parameters such as offset error, gain error, static integral non-linearity (INL), differential non-linearity (DNL), etc., cannot directly be applied. For telecommunication applications, it is the dynamic performance that usually deter- mines the quality and behaviour of the DAC [3]. Some of the most important frequency-domain performance parameters are spurious-free dynamic range (SFDR), inter-modulation distortion (IMD), signal-to-noise ratio (SNR) and signal-to-noise-and-distortion ratio (SNDR, or SINAD). There are many publications on DACs [4-14], but early publications were focused on determining and improving the static performance [4-6]. Some publications also focused on the dynamic per- formance of DACs [7-11], but the performance is far below what would be expected from ideal DACs. When measuring a 10-bit DAC we detected an SFDR larger than 65 dB (below the noise floor), even with a 1.5 V supply in standard digital CMOS [12]. With the common assumption that small transistor matching in a standard digital CMOS is pretty low (0.1 ~ 1%), how could an SFDR larger than 65 dB be achieved? This made us rethink how mismatch and certain design parameters influence the dynamic range. For a given process, can we derive a design guide to meet the dynamic performance requirements such as the SFDR and SNR? This paper adresses all these questions. Following this discussion, we will present in Sec. II the structure of the DAC modelled in this paper. In Sec. III we will discuss the influence of finite output impedance on the SFDR. In Sec. IV the influence of mismatch will be considered. In Sec. V we will discuss the influence of circuit noise on SNR. In Sec. VI we give a short description how the slewing is dependent on the signal. Sec. VII summarizes the design guide given in the paper and Sec. VIII concludes this paper. Mathematical proofs will be given in appendices. The terminology used in this paper are the fol- lowing