POWER CONSUMPTION ESTIMATION MODELS FOR FIR DECIMATION FILTERS IN MULTI-STANDARD RECEIVERS Nadia Khouja (1) , Khaled Grati (1) , Bertrand Le Gal (2) , Adel Ghazel (1) 1 CIRTA’COM Laboratory, Ecole Supérieure des Communications de Tunis, Ariana, Tunisia 2 IMS Laboratory, Université de Bordeaux I, Bordeaux, France ABSTRACT Many communications embedded systems implement decimation filters. In particular, base-band stage in multistandard receivers is composed of cascade of deci- mation filters performing channel selection. The number of used filter and the kind of these filters can have a sig- nificant impact on the computation complexity and power consumption of multistandard receivers. In This work we present FIR filters’ power consumption estimation models. Models were obtained from a large number of FIR filter syntheses using direct and polyphase forms. Several curves that estimate power consumption were extracted from these experimental results. The idea behind this work is to use the obtained models and curves to help filter de- signer to make the right choice regarding decimation fac- tor versus power consumption. Index Terms— Multistandard receiver, decimation filter, power consumption, polyphase decomposition, estimation model 1. INTRODUCTION Nowadays, wireless technologies are widespread thanks to their flexibility of use. However many different standard are used and the new challenge of the communication Em- bedded system designer is to implement multiple commu- nication standards devices providing easy access to infor- mation everywhere with low hardware complexity. In general, in such devices, communication chains include decimation and selector filters. Typically, multiple stan- dards communication chains are composed of RF front-end followed by an over-sampler analog to digital converter then by a cascade of decimation filters (Fig. 1) [1]. RF filter Analog to Digital Converter FIR decimation filter Figure 1. General communication chain in a multi-standard re- ceiver The power consumption is an important constraint during embedded system design. Hence, the design of decimation filters has a deep impact on the power consumption in multi-standard receiver. FIR filters are used to perform decimation and channel selection filters because they guar- antee linear phase. The poly-phase form of FIR filters is widely recommended for reducing power consumption in comparison to all possible implementation forms of these filters. However, we were not able to find in the literature a clear study based on experimental results showing how much power consumption FIR filters consumes and how much poly-phase form could save. In fact, we found that the reference [2] is widely mentioned. But this work deals only with power consumption, area and critical path of a particular implementation of comb filter. It was shown in this work that appropriate filter decomposition in associa- tion with poly-phase decomposition could lead to an im- portant power consumption of the Comb filter. The idea of this paper is to give models evaluating FIR decimator filters power consumption in direct form and polyphase implementation form. These models take into consideration main filter parameters: filter order, input wordlength and coefficient wordlength. The impact of the poly-phase decomposition form on the power consumption and area occupation for FIR filters is deeply studied in this work in ASIC technology and using a 65-nm low power library of STMicroelectronics. The objective of the study is to help filter designer to decide about the best way to decompose the filter process- ing into stages in order to guarantee optimal power con- sumption. This paper is organized as following: Section II presents the methodology used to estimate both power consumption and area occupation of FIR filter. In section III, we present the obtained results for direct implementation form on ASIC technology using a 65-nm STMicroelectronics li- brary. In section IV, we discussed results obtained for the polyphase implementation form in the same ASIC technol- ogy. Finally, conclusions are given in section V. 2. DECIMATOR FIR FILTER POWER CONSUMPTION CHARACTERIZATION When designing a FIR channel selection and decimation filter, filter designer faces a trade-off between channel se- lection efficiency and filter complexity. In fact, the design has to guarantee an appropriate selection of the useful sig- 2011 IEEE GCC Conference and Exhibition (GCC), February 19-22, 2011, Dubai, United Arab Emirates 978-1-61284-119-9/11/$26.00 ©2011 IEEE 617