Reduction of Conducted Electromagnetic Interference in SMPS using Programmable Gate Driving Strength A. Shorten, A.A. Fomani, W.T. Ng The Edward S. Rogers Sr. Electrical and Computer Engineering Department University of Toronto Toronto, Canada ngwt@vrg.utoronto.ca H. Nishio, and Y. Takahashi Fuji Electric Systems Co. Ltd., 4-18-1, Tsukama, Matsumoto, Nagano 390-0821, Japan nishio-haruhiko@fujielectric.co.jp Abstract— A gate driver IC with programmable driving strength to reduce conducted electromagnetic interference (CEMI) in SMPS is presented in this paper. The solution presented is to dynamically adjust the gate driving strength (output resistance R out ) at the arrival of each gate pulse to minimize CEMI while maintaining low switching loss. Dynamically adjusting R out is not possible with conventional gate driver designs. A segmented gate driver is designed and fabricated in the AMS 0.35μm 40V HVCMOS process. Unlike snubber circuits, the proposed method does not require extra discrete components or wasted energy. Experimental results indicate up to a 7dBμV improvement in peak CEMI between 20 MHz and 30 MHz. I. INTRODUCTION Despite the tremendous benefit in efficiency that SMPS can achieve over other energy conversion techniques, SMPS can exhibit a significant penalty in terms of undesired switching noise [1]. This noise takes the form of both conducted and radiated electromagnetic interference and can cause circuits near (or connected to) the converter to malfunction. This phenomenon necessitates either expensive, bulky shielding, filtering or novel techniques to reduce this unwanted interference. Traditional SMPS design strategies encourage the selection of a gate driver with the best rise and fall times. This characteristic is achieved with a low gate driver output resistance R out which is often described as a high driving strength. However, with a low R out , the gate voltage of the power MOSFET has a tendency to ring at the rising or falling edge of the input signal. This ringing also appears at the output switching node, generating undesired conducted electro-magnetic interference (CEMI). The amount of ringing is heavily influenced by R out , as it sets the damping ratio of the RLC circuit formed by the gate driver, the PCB trace and the power MOSFET (see Figure 1). By setting R out to be very large, CEMI can be reduced. However, a large R out will also increase the time required for the gate capacitance C g to charge and discharge; increasing the T on and T off times of the power MOSFET and subsequently increasing the switching loss due to shoot through current. A trade-off exists between switching loss, dead time and CEMI in SMPS [1]. This work is aimed at providing a new degree of freedom for this trade- off. In this paper, an adjustable gate drive strength technique is implemented which utilizes a segmented gate driver IC in order to reduce CEMI. Figure 1 presents the topology of the gate driver circuit, which is composed of seven identical gate drivers connected in parallel that can be individually enabled or disabled digitally on-the-fly. Through this structure, R out can be controlled in real time. During a gate transition, a reduction in CEMI is realized with little reduction of efficiency by initially driving the power transistors with a low R out and then increasing R out once the transition has passed. Furthermore, this adjustable driving strength approach is well suited for digitally controlled DC-DC converters. Section II describes the topology and the signal timing of the gate driver. The experimental test setup is discussed in Section III. Experimental results are presented in Section IV. Conclusions are discussed in Section V. * This work was supported in part by the Natural Science and Engineering Research Council of Canada, Auto21, and Fuji Electric Systems Co. Ltd. Fig. 1. Topology of the proposed segmented gate driver IC. 978-1-4244-8424-9/11/$26.00 ©2011 IEEE 364 Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC's May 23-26, 2011 San Diego, CA