Rajeev Kumar Mishra, Madhurendra Bensan, Roopesh Singh / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 3, May-Jun 2012, pp. 237-241 237 | P a g e Stress Analysis and Temperature Impact of Negative Bias Temperature Instability (NBTI) on a CMOS inverter circuit Rajeev Kumar Mishra 1 , Madhurendra Bensan 2 , Roopesh Singh 3 Department of Electronics Indian Institute of Technology, Banaras Hindu University Varanasi, India ABSTRACT- Negative Bias Temperature Instability(NBTI) has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. As the Integrated Circuits (IC) density keeps on increasing with the scaling of CMOS devices in each successive technology generation, stress analysis or reliability concerns mainly Negative Bias Temperature Instability (NBTI) becomes a major challenge. Stress Analysis becomes important for any digital circuit as it predicts the life time of the circuit in terms of the degradation of device parameters. NBTI degrades the performance of a PMOS transistor under a negative gate stress. The after effects of NBTI include: (a) threshold voltage increase of PMOS transistor, (b) drain current degradation, and (c) speed degradation. Elevated temperature and the negative gate stress play an important role in degradation of Gate Oxide. Before any circuit design Stress Analysis becomes important for any device in order to get the complete performance of the circuit. Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper basically we have studied the Stress Analysis and the impact of temperature of NBTI on a CMOS inverter circuit. Keywords - EZwave, Inverter, NBTI, Reliability, Stress, Threshold Voltage, Temperature I. INTRODUCTION The sustained growth in Integrated Circuits (IC) density and speed has been accomplished by CMOS scaling. The scaling reduces gate oxide thickness in each successive technology generation. Industrial data reveal that as oxide thickness reaches 4nm, reliability concerns (especially NBTI) becomes a major challenge [1, 2]. NBTI occurs under negative gate voltage (e.g., V gs = -V DD ) and is measured as an increase in the magnitude of threshold voltage. It mostly affects the PMOS transistor [3] and degrades the device drive current, circuit speed, noise margin, and other factors. The threshold voltage change caused by NBTI for the PMOS transistor has become the dominant factor to limit the life time, which is much shorter than that defined by hot-carrier induced degradation (HCI) of the NMOS transistor. NBTI degradation in MOSFETs is explained by the reaction-diffusion model described in next section. Stress analysis involves, studying the NBTI effect on a PMOS transistor when it is conducting. It is well known that NBTI impacts PMOS transistors during circuit operation, and the degradation occurs when PMOS transistor is in a conducting state. So, accurate NBTI degradation analysis requires analysis of logic states. Degradation of specific PMOS transistor depends on part of lifetime, in which this transistor is under stress, in other words, on stress probability. The NBTI occurs when the PMOS transistor is negative biased, in particular at elevated temperature. For a CMOS inverter circuit as shown below figure 1 represents the stress and relaxation phase when gate voltage is zero (V G =0) and V DD (V G = V DD ) respectively. Figure 1: Pulse showing stress and relaxation phase of a PMOS For a PMOS transistor, there are two phases of NBTI, depending on its bias condition. These two phases are illustrated in Fig. 1, assuming the substrate is biased at V DD . In Phase I, when Vg=0 (i.e., Vgs = -V DD ), positive interface traps are accumulating over the stress time with H diffusing towards the gate. This phase is usually referred as “stress” or “static NBTI”. In Phase II, when Vg=V DD (i.e., Vgs=0), holes are not present in the channel and thus, no new interface traps are generated; instead, H diffuses back and anneals the broken Si- H. As a result, the number of interface traps is reduced during this stage and the NBTI degradation is recovered. Phase II is usually referred as “recovery” and has a significant impact on the estimation of NBTI during the dynamic switching. Static NBTI (i.e. under constant voltage (DC) stress condition) leads to a severe threshold voltage (V T ) shifts, while the mechanism was described in [4]. However, because of associated recovery phenomena the dynamic NBTI (i.e., under AC stress), a less