Innovative Systems Design and Engineering www.iiste.org ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 3, No 1, 2012 1 Proposed Thermal Circuit Model for the Cost Effective Design of Fin FET A K M Kamrul Hasan, MD. Nizamul Islam, Dewan Siam Shafiullah Islamic University of Technology (IUT) Gazipur, Bangladesh. Abstract The Complementary metal-oxide-semiconductor (CMOS) device has been rapidly evolving and its size has been drastically decreasing ever since it was first fabricated in 1960 [Us Patent 3,356,858: 1967]. The substantial reduction in the CMOS device size has led to short channel effects which have resulted in the introduction of Fin Field Effect Transistor (FinFET), a tri-gate transistor built on a silicon on insulator (SOI) substrate. Furthermore, due to the geometry of the FinFET the severity of the heating problem has dramatically increased. Self-heating in the 3-dimensional FinFET device enhances the temperature gradients and peak temperature, which decrease drive current, increase the interconnect delays and degrade the device and interconnect reliability. In this work we have proposed a methodology to develop an accurate thermal model for the FinFET through a rigorous physics-based mathematical approach. A thermal circuit for the FinFET will be derived from the model. This model will allow chip designers to predict interconnect temperature which will lead them to achieve cost-effective design for the FinFET- based semiconductor chips. Keywords: Bulk CMOS, SOI CMOS, FinFET, Thermal heating. 1. Introduction Majority of integrated circuits produced in CMOS technology are based on a pair of complementary MOSFETs including n-channel and p-channel field effect transistors. The n-channel device employs a sufficiently high positive voltage to the gate with respect to the source, and electrons are then attracted to the semiconductor surface to establish a conductive n-channel between the source and drain, making current flow possible. The gate voltage necessary to form the channel is called the threshold voltage (V T ). However, the p-channel device requires a negative gate voltage for a conductive p-channel. Over the past 15 years, the number of devices in a single chip is approximately doubled, and the number density of devices has been significantly increased. Thus, the power density has been increasing rapidly, approaching air cool limit. The transistor channel length has decreased almost 3 orders of magnitude in approximately 30 years. However, the reduction of horizontal dimensions (such as gate length and metal width) must be accompanied by an appropriate reduction of vertical ones (such as oxide gate thickness and device channel thickness), as well as increased doping and lowered supply voltage [1]. The negative effects of failing to meet these criteria will be explained in greater detail later in this proposal. 2. Advantages of SOI CMOS over Bulk CMOS The term SOI means Silicon On Insulator structure, which consists of devices on silicon thin film (SOI layers) that exists on insulating film. Figure1 illustrates an outline sketch of bulk, partial depletion type and complete depletion type SOI-MOS (Metal Oxide Semiconductor) transistor structure. In the case of bulk CMOS devices, P/N type MOS transistors are isolated from the well layer. In contrast, SOI-CMOS devices are separated into Si supporting substrate and buried oxide film (BOX). Also, these devices are structured so each element is completely isolated by LOCOS (Local Oxidation of Silicon) oxide film and the operating elements area (called the SOI layer) is completely isolated by insulators. Also, elements that have a thin SOI layer (normally <50 nm) and have all body areas under the channel depleted, are called complete depletion type SOI. Conversely, elements that have a thick SOI layer (normally >100 nm) and have some areas at the bottom of the body area that are not depleted, are called partial depletion type SOI.