600 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 12, DECEMBER 2001 Improved Latch-Up Immunity in Junction-Isolated Smart Power ICs With Unbiased Guard Ring Sandhya Gupta, Member, IEEE, J. C. Beckman, Member, IEEE, and S. L. Kosier, Member, IEEE Abstract—The performance of the unbiased guard ring struc- ture is measured and the effects of high current, emitter area, and layout of unbiased guard rings are reported and explained. Mea- surements show a reduction in parasitic gain by up to six orders of magnitude, while also avoiding the cross talk and power consump- tion of biased rings. A comparative analysis of unbiased guard ring with biased guard ring shows up to 100 times better performance at low current levels. A modification to the unbiased guard ring is also implemented and successfully tested which shows an increase in the current handling capability of the structure by an order of magnitude. Index Terms—Crosstalk, crosstalk isolation, current carrying capability, high voltage LDMOS, isolation technology, latch-up, latch-up immunity, low-voltage CMOS control circuit, power IC technology. I. INTRODUCTION S MART power ICs integrate high-voltage, high-power transistors with low-voltage, low-power control circuitry in order to reduce cost while increasing performance and reliability. Unfortunately, this integration risks latch-up from the injection of minority carriers into the substrate by a forward biased n-tub-to-substrate junction of a high-power device. To prevent latch-up by reducing the gain of the parasitic substrate NPN that injects and absorbs minority substrate carriers, both biased and unbiased guard rings, which surround the high-voltage device, have been proposed [1], [2] and several other techniques for latch-up prevention have been studied [3]–[7]. Unbiased guard rings are preferable because they avoid the cross-talk, power consumption, and interconnect requirements of biased guard rings, but unbiased rings are less understood. This letter reports and explains measurements of the comparative performance, high-current effects, emitter area, and layout of unbiased guard rings. It also shows a layout modification to the unbiased guard ring structure which increases its current handling capability and makes it very attractive for smart-power IC layout. II. LATCH- UP PROTECTION UNBIASED GUARD RING The cross section and layout view of the unbiased guard ring structure is shown in Fig. 1. The unbiased guard ring is a set of three rings surrounding the emitter, E , which is the n-tub body Manuscript received July 2, 2001; revised September 18, 2001. The review of this letter was arranged by Editor J. Sin. The authors are with PolarFab, Bloomington, MN 55425-1350 USA (e-mail: GuptaS@PolarFab.Com). Publisher Item Identifier S 0741-3106(01)10784-6. Fig. 1. (a) Cross section and (b) layout view of the unbiased guard ring structure. The unbiased guard ring reduces the gain of the parasitic lateral NPN shown in figure (a). For clarity, only a small piece of the thin metal short is shown in the figure. In the actual layout, the metal short is a complete ring, connecting the two rings all the way around the device. of a power device that is expected to be driven below ground by events such as the switching of an inductive load. The inner- most ring, B - , is a substrate contact (SubCon) ring that is tied to ground. The middle ring, C , is an n-tub contact ring. The outermost ring, B - , is a SubCon ring. The middle and outermost rings are shorted together, but are unbiased, meaning that they are not connected to any other part of the circuit, ex- cept through the substrate. The guard ring is designed to protect all other n-tubs on the chip (e.g., C ) from acting as collectors for minority carriers injected into the substrate by E . 0741–3106/01$10.00 © 2001 IEEE