1 A 12-bit 20MS/s 56.3mW Pipelined ADC with Interpolation-Based Nonlinear Calibration Jie Yuan, Member, IEEE, Sheung Wai Fung, Kai Yin Chan, and Ruoyu Xu, Student Member, IEEE, Abstract—The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35m 3.3V CMOS process. The ADC samples at 20MS/s. The calibration improves the ADC DNL and INL from 1.47LSB and 7.85LSB to 0.2LSB and 0.27LSB. For a 590kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3dB and 52.1dB to 72.5dB and 84.4dB respectively. The 11.8-ENOB 20MS/s ADC consumes 56.3mW power with 3.3V supply. The 0.78pJ/step figure-of-merit (FOM) is low for designs in 0.35um CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8dB due to the slow settling of the first pipeline stage. Index Terms—Pipelined ADC, high-resolution pipelined ADC, MDAC, linear error, nonlinear error, digital calibration. I. INTRODUCTION OW-power high-resolution (12~14bit) pipelined ADC is important in modern applications of telecommunication, consumer electronics and medical electronics. Various power reduction techniques have been developed for low-resolution (8~10bit) pipelined ADCs, such as OPAMP sharing ([1]-[4]), switched-OPAMP ([5]), and pseudo-differential ADC ([6]- [9]). Even low-power comparator was used as the residual amplifier ([10],[11]). However, these techniques are difficult to apply for high resolution pipelined ADCs. Manuscript received June 28, 2011. This work was supported in part by the grant from the ITC of Hong Kong Special Administrative Region Government (Reference No. ITS/156/09). Authors are with the Electronic and Computer Engineering Department, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong (corresponding author to provide phone: +852-2358-8029; fax: +852-2358-1485; e-mail: eeyuan@ ust.hk). Pipelined ADCs with resolution higher than 12 bit generally consume large power due to stringent requirements on capacitance mismatch and OPAMP gain ([12],[40]). Capaci- tance mismatch and low OPAMP gain leads to both linear and nonlinear error in the MDAC, which causes the pipeline nonlinearity ([6],[13],[22]). Therefore, the capacitor size in high-resolution pipelined ADCs is typically much larger than the noise-limited (kT/C) size to achieve the tiny capacitance mismatch. To reduce the MDAC error from the capacitance mismatch and low OPAMP gain, majority of high-resolution pipelined ADC designs use either trimming ([12], [14], [15]) or calibration. Most calibration techniques are developed to compensate for linear error ([16]-[21]) by measuring or estimating the actual MDAC gain. A group of nonlinear calibration techniques have been developed to compensate more significant MDAC error with signal-dependent gain([13],[22]-[30]). In [23]-[25], an accurate ADC was used to calibrate a single nonlinear MDAC by estimating the 3 rd -order harmonic term. Higher order terms were estimated in [41]. Significant power reduction was demonstrated in [23],[24]. However, complicated adaptation algorithms, such as least-mean-square (LMS), are needed for the estimation of MDAC parameters. A digital processor with 8.4K gates was needed in [23]. The LMS loop also poses trade-off between step size and convergence speed, which leads to convergence time>100ms. Scalability is another major problem of these adaptation-based nonlinear calibration techniques. Adaptation-based nonlinear calibration techniques were developed for pipelined ADC with multiple nonlinear MDACs in [13],[25]-[30]. The complexity of the estimation problem increases quickly, which leads to longer convergence and larger digital calibration processor. Backend ADC was used to measure nonlinear MDACs in [26]-[28]. However, the backend quantization error can accumulate to corrupt the estimation accuracy[28]. In [26],[30], the backend quantization error also needs more cycles to decorrelate it from the input random sequences, which extends the convergence to billions of cycles. The digital processor also required at least 4 multipliers for every nonlinear MDAC. The LMS adaption process in [27] requires millions of cycles to converge, and 62K gates for the digital processor. A separate ADC channel was used to measure the main pipeline in [13], [29]. In both designs, the LMS adaptation ran with the whole pipeline estimated by L Copyright (c) 2011 IEEE. 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