Using static timing analysis and verification engines to generate native-mode tests for small delay defects Sankar Gurumurthy, Ramtilak Vemu and Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin {sankar, rvemu, jaa}@cerc.utexas.edu Daniel G. Saab Dept. of EECS Case Western Reserve University saab@eecs.cwru.edu Abstract— With shrinking process technologies, small delay defects are becoming more prominent. Therefore, there is a need to test processors for such defects. However, structural tests for delay defects may lead to considerable yield loss. Moreover, prevalent fault models for delay defects are not efficient in terms of either representing the defects adequately or in the effort required to achieve good coverage. In this paper, we present a technique which generates instruction sequences targeting small delay defects. We use a fault model called improved unified fault model (IUFM). The instructions generated by our technique can be loaded into cache to test the processor in native mode. I. I NTRODUCTION Studies [1] show that with decreasing process parameters, defects like resistive opens are becoming more common. These defects are called delay defects because they cause changes in the overall delays of the circuit. They can be classified as either gross delay or small delay defects, depending on the amount of change in delay caused. The small delay defects affect only the longer paths in the circuit. They cause those paths to fail the setup time requirements. Small delay defects can also be caused by process variations. The chips in the slower corner will have a similar behavior to that of chips with small delay defects. Scan based techniques have been used till now with good success in testing for non-delay defects. However, research [2] shows that a large portion of structurally testable delay faults are actually functionally unsensitizable. Hence, using scan for delay testing can lead to considerable yield loss due to overtesting. Native-mode testing [3] provides a better way for testing small delay defects. It loads instruction sequences into cache and tests the processor in its native-mode (or regular functioning mode). Since only legal instruction sequences are used to test the processor, chips that fail these tests are definitely defective. Hence, there is no yield loss. However, currently there are no automated methods that produce in- struction sequences targeting delay fault models. We address that problem in this paper. A good fault model is essential for any testing methodology. The stuck-at fault model can not adequately portray the effects of delay defects. Path delay fault model [4] is a good way to model the small delay defects, especially the effects of distributed defects. However, it is difficult to achieve good coverage using it, since all the paths in a circuit (potentially exponential in number) need to be covered in this model. A new fault model, called improved unified fault model (IUFM), was proposed in [5]. It involves generating tests for the longest sensitizable path (both rising and falling) passing through all the nets and also all the sensitizable paths above a certain threshold in the circuit. The number of longest paths through each net is linear in terms of the number of nets in the circuit. Moreover, by choosing an intelligent threshold, it is possible to represent the effects of distributed small delay defects and also test for only a moderate number of paths. Therefore, it is easier to achieve higher coverage using this fault model. Hence, this fault model provides a good framework to target small delay defects. We validate our technique using IUFM. Our technique uses static timing analysis (STA) and verification engines. The STA engine is used to come up with the long paths. We then generate instruction sequences for those paths. We consider both the controllability and observability aspects of the test generation process. We express the constraints required for both as linear temporal logic (LTL) [6] property. We then pass (negation of) this property to a bounded model checker. We also automatically transform the model to make property specification easier. Bounded model checkers unroll the model up to a given bound and verify the given property within that bound. They produce a counterexample (error trace) if the property can be falsified within the given bound. We also give the constraints based on instruction set architecture (ISA) to the bounded model checker. If a counterexample is produced by the bounded model checker, the instruction sequence for exciting and propagating the path effects is present in the counterexample. If no counterexample is found then no instruction sequence exists within the given bound. In summary, we propose a automated method for gener- ating instruction sequences targeting small delay defects in a processor using static timing analysis and verification engines. This is very pertinent in the current trend of processes because the delay defects are becoming and native mode testing is needed to test for them without causing yield loss.The paper is organized as follows. We provide relevant work in the literature in Section II. Section III gives the necessary background. Our technique is explained in Section IV. We describe our experiments in Section V. The conclusions and the areas for further work are discussed in section VI.