Functional specification for a Time Management Unit Kristoffer Nyborg Gregertsen, Amund Skavhaug Department of Engineering Cybernetics, NTNU N-7491 Trondheim, Norway {gregerts,amund}@itk.ntnu.no Abstract This paper gives a functional specification for a Time Management Unit (TMU) used to support ex- ecution time control in real-time systems. The TMU is designed for efficient access though the high-speed bus (HSB) of the microcontroller. The simplicity of the described TMU allows it to be added to existing System-on-Chip (SoC) designs with minimal effort. 1. Introduction Real-time scheduling algorithms usually depend on the worst-case execution time (WCET) of tasks being known in order to guarantee for all deadlines be- ing reached. For modern computer architectures using performance enhancing techniques such as pipelines, cache and branch prediction, finding this WCET may be very hard [1], and therefore prohibitively expensive and time consuming for most embedded projects. Also the WCET will often be much greater than the average execution time. Given that the WCET is not known the developer has to choose whether to use conservative budgets and have poor CPU utilization, or to use op- timistic budgets and risk deadlines occasionally being lost. Neither of the alternatives may be acceptable. By using execution time control developers may use less conservative budgets and handle overruns dynamically in order to prevent deadline loss. In order to do this the run-time system has to provide execution time clocks that measure the total time an executable entity has been running on the system. The clock is started when the entity is scheduled for execution and stopped when it is done executing or preempted by another entity. A timer is associated with a clock and is used to call an event handler when its clock reaches a specified time. We will refer to clocks and timers combined as execution time monitoring. Execution time monitoring for Ada 2005 was im- plemented on the AVR32 architecture by the authors at NTNU [2]. Our implementation differs from other implementations known to the authors by not charging the interrupted task the execution time of interrupt handlers. This time was instead charged a pseudo interrupt task for the given interrupt priority. The benefits of doing this are twofold: (1) The accuracy for task execution time measurement is improved, allowing tighter task budgets, and thereby higher CPU utilization. (2) It is possible to monitor and control the execution time spent on handling interrupts of a given level. This makes it possible to protect the systems from bursts of interrupts that could otherwise result in tasks missing their deadline. For these features to be efficient the overhead of switching clocks when entering an interrupt handler and performing a context switch should be as low as possible, preferably also with a deterministic execution time. The AVR32 implementation of execution time monitoring used the CPU cycle COUNT / COMPARE system registers of the architecture. Since these regis- ters are only of 32-bits, relative time had to be used resulting in computational overhead when translating the absolute execution time into a relative one. Spe- cial care was also needed to prevent COUNT from overflowing. The lack of timers that allow sufficient efficiency for execution time monitoring motivates a dedicated timer unit which we will refer to as a Time Management Unit (TMU). A TMU for the LEON architecture has been de- signed at NTNU and implemented on a FPGA [3]. This design is more complex than the one described in this paper. This TMU has the IRQ lines as input from the interrupt controller and forwards these to the core. The active timer is changed according to the run- level. Therefore it has one set of COUNT / COMPARE registers for the ordinary execution level and each interrupt level. If the budget for an interrupt level is exhausted it is masked, and the CPU would not handle interrupts of this level until the budget is replenished. The replenishing of interrupt execution time budgets is