Institute of Advanced Engineering and Science w w w . i a e s j o u r n a l . c o m International Journal of Information & Network Security (IJINS) Vol.1, No.2, June 2012, pp. 119~126 ISSN: 2089-3299  119 Journal homepage: http://iaesjournal.com/online/index.php/ IJINS A Reconfigurable Cryptography Coprocessor RCC for Advanced Encryption Standard AES/Rijndael S. El Adib, N. Raissouni, A. Chahboun, A. Azyat, M. Lahraoua, N. Ben Achhab, A. Abbous, O. Benarchid Innovation & Telecoms Engineering Research Group. Remote Sensing & Mobile GIS Unit. University Abdelmalek Essaadi. Mhannech II, B.P 2121 Tetuan, Morocco Article Info ABSTRACT Article history: Received Jun 12 th , 2012 Revised Jun 20 th , 2012 Accepted Jun 26 th , 2012 The market trend of secure products is to offer more users' services and security. Thus, electronic devices must be flexible and reconfigurable in the way they permit executing further algorithms than those designed for. In this paper, in order to encrypt/decrypt data blocks, a Reconfigurable Cryptography Coprocessor (RCC) for Advanced Encryption Standard (AES/Rijndael) is developed. The AES offers a good combination of security, performance, efficiency, implementability and flexibility. We propose a RCC by using a Systolic Processor (SP) based on: i) Processing Element (PE) array, and ii) Controller with a Finite State Machine (FSM) and a memory. The advantages are: i) provide a solution to compute all matrix format data and ii) the PE array's data path is reconfigurable via the FSM. Finally, the conception and implementation were carried out by using Very High Speed Integrated Circuit Hardware Description (VHDL) language and Xilinx ISE 7.1 simulator. Keyword: Security AES FPGA Reconfig. Crypto Processor VHDL-Xilinx Copyright @ 2012 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Naoufal Raissouni, Ph.D, National School for Applied Sciences of Tetuan, Abdelmalek Essaadi University, Innovation & Telecoms Engineering Research Group. Remote Sensing & Mobile GIS Unit, Mhannech II, B.P 2121 Tetuan, Morocco. Email: nraissouni@uae.ma 1. INTRODUCTION Security of data is becoming an important challenge for a wide spectrum of applications, including communication systems secure storage supports, digital video recorders, smart cards, cellular phones [1]. Most of encryption and decryption models are implemented for specific algorithm. It is easy to implement hardware for a single algorithm. With such models, it is not possible to treat different encryption algorithms [2], furthermore the corresponding market is now oriented towards more flexibility. Thus, electronic devices must be flexible and reconfigurable in the way they permit executing further algorithms than those designed for. The main objective of the present paper is to design a module of a reconfigurable cryptographic coprocessor capable of executing on Advanced Encryption Standard (AES/Rijndael) [3], [4], [5] and using the basic arithmetic and logic operations. VHDL and logic synthesis tools have been used to design RCC. RCC Architecture is based on 4x4 Processing Elements (PE) systolic array [6]; it belongs to the class of the flexible hardware implementations, and allows a user implementing other cryptographic algorithm under specific conditions. Finally, test results and performance evaluation is presented.