©2010 International Journal of Computer Applications (0975 – 8887) Volume 1 – No. 14 92 Power-Estimation for on-Chip VLSI Distributed RLC Global Interconnect using Model Order Reduction Technique R. Kar VLSI Laboratory Department of ECE NIT Durgapur-713209 V. Maheshwari VLSI Laboratory Department of ECE NIT Durgapur-713209 Ashis K. mal VLSI Laboratory Department of ECE NIT Durgapur-713209 A.K.Bhattacharjee VLSI Laboratory Department of ECE NIT Durgapur-713209 ABSTRACT Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced- order model [1]. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – Simulation; General Terms Algorithms, Design, Theory Keywords Power estimation, Model Order Reduction, RCL Interconnect, Moment matching 1. INTRODUCTION As the scale of process technologies steadily shrinks and the size of designs increases, interconnects have increasing impact on the area, delay, and power consumption of circuits. Over the past decade there have been a number of advances in modeling and the analysis of interconnect that have facilitated the continual advances in design automation for systems of increasing size and frequency. As integrated circuit feature sizes continue to scale well below 0.18 μm [2], active device counts are reaching hundreds of millions. Interconnect models must incorporate distributed self and mutual inductance to accurately estimate time delay and crosstalk in a multilevel network for multi-GHz gigascale integration (GSI) [3]. In addition to interconnect delay, crosstalk noise resulting from capacitive and, more recently investigated, inductive effects [4], [5] between adjacent interconnect lines is also becoming a primary concern for ICs performance and reliability. Furthermore, with present VLSI technology, on-chip interconnects are best modeled as a network of coupled lines the amount of interconnect among the devices tends to grow super linearly with the transistor counts, and the chip area is often limited by the physical interconnect area. Due to these interconnect area limitations, the interconnect dimensions are scaled with the devices whenever possible. In addition, to provide more wiring resources, IC’s now accommodate numerous metallization layers, with more to come in the future. These advances in technology that result in scaled, multi-level interconnects may address the wire ability problem, but in the process create problems with signal integrity and interconnect delay. As regards power, the situation is similar in that the portion of power associated with interconnects is increasing. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. Furthermore, the power consumed by interconnects results in a phenomenon, called self heating, which reduces electro-migration induced mean time to failure (MTF) [6]. It is shown in [7] that the power distribution analysis on interconnects is feasible in frequency domain using poles and residues. However, high complexity is inevitable when calculating the power dissipation of the whole interconnects since poles and residues of the current flowing through each element have to be calculated. As feature sizes are decreased to deep sub-micrometer dimensions, on-chip interconnect is best modeled as a distributed RLC line. However, unlike the RC model, such a model increases the complexity of interconnects crosstalk noise and its induced delay estimation. Advances in deep sub-micron technology indicate that present and future interconnects might no longer be considered as simply made of RC lines. Thus, RLC interconnect models become a necessity [8]. It therefore appears that, if accurate interconnect delay estimation is to be achieved, modeling interconnect as a distributed RLC line is necessary. In this case, the commonly and generally well-accepted Elmore delay calculation becomes inapplicable to RLC interconnect networks due to their non- monotonic characteristics induced by inductances [8] [9]. To verify the effects induced by interconnects a combination of extraction and analysis is necessary. Extraction determines the capacitance and the resistance of interconnects, which can then be used to build a circuit model for the analysis of interconnect effects. For analysis (or estimation), extensive studies have been made of the use of model order reduction over the last few years, following the introduction of AWE [9]. Model order reduction is based on approximating the Laplace-domain transfer function of a linear network by a relatively small number of dominant poles and zeros. Such reduced-order models can be used to predict the time- domain or frequency-domain response of the linear network. Power, which inherently involves improper integration, can be derived from the poles and residues of the transfer function, which requires only algebraic computation. When the interconnect is driven by MOSFETs and connected to the gates of MOSFETs, the