0-7803-8906-9/05/$20.00 ©2005 IEEE 2005 Electronic Components and Technology Conference Stencil Printing Technology for Wafer Level Bumping at Sub-100 Micron Pitch using Pb-Free Alloys R. W. Kay* 1 , E. de Gourcuff 2 , M. P. Y. Desmulliez 1,2 1 MicroStencil Limited, 20 Lee Crescent, Edinburgh, EH15 1LW, UK 2 MIcroSystems Engineering Centre (MISEC), School of Engineering & Physical Sciences, Heriot-Watt University, Edinburgh, EH14 4AS G. J. Jackson*, H. A. H. Steen Henkel Technologies, Kelsey House, Wood Lane End, Hemel Hempstead, Hertfordshire HP2 4RQ, UK C. Liu, P.P. Conway School of Mechanical and Manufacturing Engineering, Lougborough University, Loughborough, LE11 3TU, UK * Corresponding Authors: r.w.kay@micro-stencil.com; gavin.jackson@uk.henkel.com Abstract In this paper solder paste printing is reported at sub 100µm pitch using Pb-free solder paste with IPC type-6 (15- 5µm) particle size distributions. The results confirm that consistent sized paste deposits can be produced onto wafers at ultra fine pitch geometries using a stencil printing process. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have on the reproducibility of the deposits. The investigation also reveals that the volume of solder paste deposit can be controlled by selecting different shapes of stencil apertures. Large volumes of paste are required during reflowing of the fine particle solder paste to produce sufficient stand-off between the flip chip device and substrate. Print consistency and uniformity of the bumps generated are also governed by the volume of solder paste for each deposit. Statistical examinations of printing defects from a large number of printing trials have been conducted for several bump geometries. Subsequently the best print parameters were then used to print onto wafers containing bond pads so the paste deposits could be reflowed to form solder spheres for analysis. This advancement in the stencil printing process at ultra fine pitch has been made possible by refinements to both solder paste design and stencil manufacturing technology. Adjustments in the solder paste rheology (shear thinning, tackiness and visco-elastic properties), mainly by varying the metal content and flux type, have enabled successful printing at ultra fine pitch geometries. The design of new paste material has also be conducted alongside a Design of Experiments to adjust printing parameters such as printing speed, pressure, print gap and separation speed to allow for a practical process window. Moreover, advancements in stencil fabrication methods have produced ‘state-of-the-art’ stencils exhibiting highly defined shaped apertures with smooth walls at ultra fine pitch, thus allowing for improved solder paste release at very small dimensions. Introduction Advances in chip scale packaging technologies have prompted a rapid increase in the density of solder joints in microelectronics products. Further reductions in the pitch size are likely, leading to joint structures exhibiting sub- 100µm dimensions [1, 2]. As designers take advantage of the benefits of Chip Scale Packaging (CSP), this drive promotes a shift from the traditional process of assembling the package of each individual unit after wafer dicing to packaging an integrated circuit at wafer level. This Wafer Level Packing (WLP) process has the advantages of true integration of wafer fabrication, packaging, test, and burn-in at the wafer level. WLP is essentially a true chip-scale packaging (CSP) technology, since the resulting package is practically the same size as the die. Fine dimension solder paste deposits are being driven by the rapidly increasing requirement for flip chip & direct chip attach technologies at the chip or wafer level. These packaging solutions enable products to be manufactured with joints at geometries similar to those of the semiconductor chips. Such packaging formats take advantage of the weight and space saving needs for many portable electronic devices. Moreover other advantages such as higher device efficiency, ability to utilize wafer level bumping and the minimization of cross-talk and inductance are driving the industry to adopt such technologies. As the interconnection pitch decreases below 200μm pitch the current stencil printing technology is struggling to produce the required geometries. This is pushing semiconductor manufacturers to adopt other more expensive and time consuming techniques such as electroplating, evaporation, solder jetting, stud bumping, adhesive dispensing and daubing. Each technique has demonstrated favorable attributes in terms of technological capability, yield analysis and processing costs. Stencil printing, however, has been proven to be the most economical solution for flip chip interconnection technologies [3, 4, 5]. Stencil printing has obvious advantages in particular for high volume assembly because of its high throughput and low cost. For ultra fine pitch applications stencil printing has appeared for a long time to have reached its practical limits. Further progress can only be made by improving the stencil manufacturing process, paste materials and by achieving a better understanding of the sub processes in stencil printing. Paste roll, aperture filling/release, post print behaviour and paste open time need to be considered as experimental inputs for the following parameters: fine particle Pb-free solder pastes and solder paste rheology, particle size distribution, metal content, flux type and stencil aperture attributes. The 848