Fault Resilient Galois Field Multiplier Design in Emerging Technologies Mahesh Poolakkaparambil 1 , Jimson Mathew 2 , and Abusaleh Jabir 1 Oxford Brookes University 1 , Department of Computing and Communication Technologies, Wheatley Campus, Wheatley, Oxford, UK University of Bristol 2 , Department of Computer Science, UK Abstract. Transient error is a critical issue in nano scale devices. The poten- tial replacement technologies for CMOS circuits, such as Carbon Nano-Tube Field Effect Transistor (CNTFET) based circuits and Quantum Cellular Automata (QCA), are further scaled down below 20nm. This results in computations per- formed in lower energy levels than CMOS, making them more vulnerable to tran- sient errors. This paper therefore investigates the performance of inevitable error mitigating schemes such as the Concurrent Error Detection (CED) over binary Galois Fields (GF) in CNTFETs and QCA. The results are then compared with their CMOS equivalents which are believed to be the first reported attempt to the best of the authors’ knowledge. A QCA based GF multiplier layout has been presented as well. The detailed experimental analysis of CMOS with CNTFET design proves that the emerging technologies perform better for error tolerant designs in terms of area, power, and delay as compared to its CMOS equivalent. Keywords: Galois Field (GF), Concurrent Error Detection (CED), Carbon Nano-Tube Field Effect Transistor (CNTFET), Quantum Cellular Automata (QCA), Transient Er- ror. 1 Introduction Modern day computing hardware requires much more processing power to perform complex computations efficiently and quickly than ever before. According to ITRS- 2009 surveys, it is evident that further scaling in CMOS devices is limited by the adverse performance of the devices beyond 20nm geometry. However, the emerging technolo- gies such as CNTFET’s and QCA based digital circuits may be the potential replace- ment for the classical CMOS technology to continue with this trend of integration. As these devices are scaled down beyond certain nano meters, the energy used to convey information is further reduced which in turn makes the computation more vulnerable to transients and various manufacturing faults. This is a serious issue for, among other ap- plications, stand alone cryptography hardware for example. Several decades ago, Intel reported faulty operations in their chips due to interference of radiation particles from the packaging materials [6]. Further research also proved that data processed within an integrated circuit can be analyzed and decoded using radiation effects. The impact of the resulting transient faults, either natural or malicious, in nano scale devices made up