COMPILATION OF HIGH-LEVEL LANGUAGES ONTO FINE-GRAIN FCCMs WITH EXPLOITATION OF INSTRUCTION-LEVEL PARALLELISM João M P Cardoso 1 and Horácio C Neto 2 1 Universidade do Algarve, 2 Instituto Superior Técnico, INESC-ID http://esda.inesc.pt/~jmpc, http://esda.inesc.pt/~hcn jmpc@acm.org, hcn@inesc.pt Abstract: This paper describes the achievements on the compilation of behavioral descriptions in high-level software languages to field-programmable custom computing machines (FCCMs) based on a field-programmable gate array (FPGA) with one or more attached memories. A hierarchical model to efficiently represent an high-level function previously written in the Java language is shown. The proposed model is much more efficient to represent the instruction-level parallelism (ILP) than models typically used by the high-level synthesis community. With this model, concurrent regions of the code can be scheduled considering its parallel execution. These regions can be, for instance, independent loops. This paper enumerates the analyses already integrated in the framework, ongoing and future research. Keywords: Compiler optimizations, Compilers, Computer-aided system design, Design systems, Digital systems, Parallelism, Programming support, Programmable logic devices (FPGAs). 1. INTRODUCTION The permanent increase in size and complexity of the new generation of reconfigurable devices augments the gap between design capacity and technology. New FPGA devices with upto 4 million system gates are becoming available, but tools are still in lack as far as reconfigurable computing is concerned (Cardoso and Véstias, 1999). To manage the device densities and complexities available today, the abstraction levels when describing behaviors must be higher than those provided by current hardware description languages (HDLs). Many authors believe (e.g. Babb et al., 1999) that high-level (software) languages are more appropriate to describe applications with equivalent complexity and that reconfigware (reconfigurable hardware) compilation from software languages is the most effective way to take advantage of the million-gates FPGA devices capacity. Furthermore, it permits the migration to reconfigware of already developed algorithms - mostly programmed in C/C++ and/or Java and is the key to widespread the reconfigurable computing paradigm. In the last few years we have seen time-to-markets each time more tiny and arduous to respect in part due to the increasingly demand complexities of the new systems. With the explosion of power consumption in DSPs and microprocessors majority linked to the instruction fetch-decoding, control unities and clock distribution (60-90% of the overall consumption, depending on the CPU) (Brooks and Martonosi, 1999), FPGAs may take an important role in the future systems as they have the flexibility of software combined with the specific characteristics of hardware. The advent of dynamic reconfigurability of these devices added the required temporal domain to reconfigurable computing. It seems that the increasing gap between design capacity and available resources tend to be even greater when reconfigurable computing is concerned (Becker et al., 1998). This gap has been addressed by Controlo’2000: 4th Portuguese Conference on Automatic Control ISBN 972-98603-0-0 558