NOVEL SIGNAL FLOW GRAPHS OF CURRENT CONVEYORS Dalibor Biolek VA Brno, Dept. of El. Engineering K301 Kounicova 65, PS13, 612 00 Brno, Czech Republic E-Mail: biolek@cs.vabo.cz ABSTRACT Economical signal flow graphs (SFG) of current conveyors CCII+ and CCII- are introduced in this contribution. Described method is based on the linear transformation of circuit equations with the aim to decrease their number. The evaluation of the SFG is then modest. INTRODUCTION Due to the growing role of current-mode analog signal processing, the current conveyors become important building blocks in many applications. Besides the current conveyors in the integrated circuit form, the principle of current conveyance is used in other building blocks as transimpedance OpAmps. Thanks to the firm LTP Electronics, the integrated positive current conveyor CCII01 is currently available [1]. As regards transimpedance OpAmps, the Analog Device's monolithic OpAmp AD 844 with compensation pin is most popular in analog signal processing [2]. Nowadays, some novel high-frequency and low- sensitivity current conveyor-based circuits are developed [1-4]. However, the effective tool for the synthesis facilitation and fast control analysis is not available. The specially modified signal flow graphs can hold this function. MODELING OF CURRENT CONVEYOR USING SFG The well-known schematic and circuit representation of current conveyor is in Fig.1. The classical circuit equations are as follows: I V I V I V Y X Z Y X Z = ± 1 1 . The sign +/- is true for the positive/negative current conveyor. 1 Y X I I Z b) X Y Z CCII + - CCII+ CCII- a) I I I Z X Y -I Fig.1. a) Black-box representation of the current conveyor, b) its circuit model. However, these equations are not suitable for the generation of appropriate SFG. Better way is to utilize modified nodal approach (MNA). Let us consider circuit in Fig.2 a). Following equations are true: ( ) ( ) ( ) ( ) ( ) ( ) ( ). 1 1 3 3 3 3 1 1 2 2 2 2 2 1 1 1 V V Y I V V Y I V V Y I I V V Y I V V Y I V V Y I V V Y I V V Y X Z Z Z X X Y Y Y X Y X - ± - = = - = - - = - = - = - = = m m The graph representations of aforementioned equations are in Fig. 2b) and c). First SFG can be used if the current I needs to be calculated. Second one represents the reduced graph where the variable I is eliminated from circuit equations. After generalization, the general rules of compiling CCII graphs are derived in Fig.3. In the reduced graph, the variables of node X are omitted. Admittances connected to this node create transmissions of branches to the output node Z and