Non-redundant Scheme for Arbitrary Error Detection in Combinational Circuits Osnat Keren, Ilya Levin and Mark Karpovsky Abstract— The paper deals with synthesis technique for de- signing circuits with on-line errors detection. We present a new technique of designing a concurrently checking functional circuit by partitioning the circuit into two independent sub-circuits. The technique does not require any redundant coding variables. Instead, we propose to utilize some input variables. These variables are transferred directly into the checker providing the self-checking property for arbitrary errors (not necessarily unidirectional). A method for constructing the overall system is presented. Benchmark results are presented and show the efficiency of the proposed approach. Index Terms— Concurrent error detection, on-line checking, combinational circuits, partitioning I. I NTRODUCTION Progress in the microelectronics industry leads to increase of complexity of VLSI schemes and components. The number of transistors in the VLSI schemes has already reached millions, and in some cases has risen even higher. Shrinkage of a device size and reduction of power supply levels, as well as the increase in operating speed has resulted in reduced noise margins [17]. The failures phenomena, together with the need for higher reliability of complex digital systems, are of special interest. As the microelectronics industry moves toward deep sub-micron technologies, systems designers have become increasingly concerned about the reliability of future devices that will have propagation delays shorter than the duration of transient pulses induced by radiation attacks. They are also concerned about smaller transistors, which will be more sensitive to the effects of electromagnetic noise, neutron and alpha particles, which may cause transient faults, even in fully tested and approved circuits [1]. Most of faults that occur in VLSI circuits and systems are transient/intermit in nature. The self-checking property allows both the transient and permanent faults to be detected, thus preventing data contamination. Systematic error-detecting coding is one of the most effec- tive instruments for concurrent error detection. This type of coding often utilize separate codes, since such codes allow preserving informational bits of the binary words to be coded, while complementing the binary words by check bits. The coded binary words form a set A of codeword. The set A can be defined either by a list of the codewords, or by a specific property distinguishing the codewords from non- codewords. In order to ensure that the codewords differ from non-codewords, each non-codeword, formed at an output of a scheme instead of a codeword a due to a specific type of fault, should either not to belong to the set A, or to be equal to the correct word in A. Models of distortion of codewords are usually built taking into account characterizing features of the stream of faults and of the scheme under checking. As it is accepted in relevant papers, we will consider that faults are manifested by pins signals of ”0” or ”1” on input or output contacts of logical elements forming the scheme to be checked. The faults can be temporary or permanent. It is traditionally accepted that a time interval between occurrences of two adjacent faults is sufficient for coping with the earliest fault. Therefore, only a single fault can present simultaneously in a scheme under checking. This fact is usually considered when building models of acceptable distortions of output codewords. Most of relevant publications use the following two models of distortions. The first model is based on an assumption that a system of functions, which reflects conversion of information in a scheme under check, is monotonous. For example, schemes that do not comprise inverters satisfy the mentioned assump- tion. In such schemes, any single fault may only result in so-called unidirectional faults of output code words [6]. The Berger code [2], and sometimes the Smith code [15] are used for detecting unidirectional errors. A number of algorithms are known [4], [5], [14], [9], which allow converting an arbitrary scheme in such a manner that the Berger code could be used for its checking. To this end, the scheme can be modified in such a way, that only its input variables become negated [4]. The works [5], [14] propose algorithms of converting the scheme under check by duplication of some of its elements. The paper [9] describes a combination of several approaches. The second model is based on an assumption that a number of distorted bits in a codeword is not greater than a prede- termined threshold t. The paper [12], based on a study of a large number of benchmarks, shows that in most of the cases a single fault results in errors in two or less bits of a codeword. The majority of the known concurrent checking schemes assumes that a set of output codewords of the functional circuit to be checked is complete, i.e., any binary vector is a codeword. However, it is often reasonable to construct a so- called context-oriented concurrent checking scheme, where: a) the number of possible codewords, is much smaller than 2 k , where k is the width of the output vector, and b) the set of possible codewords is known in advance. The context-orientation has some advantages in comparison with the universal orientation. Namely, it allows utilizing the redun- dancy of the circuit’s output codewords, which is an intrinsic feature of such circuits. One of the ways of utilizing the redundancy is by dividing the functional circuit into a number of separate independent sub-circuits. Each of these sub-circuits implements its own subset of output signals. Since the sub- circuits have no common elements, any single fault may result