Abstract— We present an SRAM hardening technique based on combining transistors with different threshold voltages to construct the basic SRAM cell structure. Such a structure maintains the number of transistors and their sizes, while improving the cell robustness. Results show that, for a 90 nm technology, this technique improves Q crit . Index Terms — SRAM hardening, SEU, Critical Charge (Qcrit), Nano CMOS I. INTRODUCTION HE reliability of sub-100-nm ICs has been dramatically reduced by the continuous device shrinking, growing circuit complexity, power supply reduction and increasing operation speeds that accompany the technological evolution of nanometric technologies. A significant problem is related to soft errors induced by alpha particles emitted by radioactive impurities present in IC components and atmospheric neutrons originating from the interaction of high-energy cosmic rays with atoms in the Earth’s atmosphere [1]. Memories represent the largest parts of modern designs. In addition, they are more sensitive to ionizing particles than logic since they are designed to reach the highest possible density. It has been reported that the soft error rate (SER) due to soft errors in modern designs is dominated by the SER of their memories [2]. Therefore, when the SER of a design is to be reduced, protecting the memories is usually the first priority. Soft error mitigation techniques include electrical-level, gate-level and architectural-level approaches. Architectural- level approaches, like error-correcting codes or triple modular redundancy and majority voting, are the most commonly used solutions in memories and in logic parts respectively. The speed and/or power and/or area penalty induced by these solutions make them unacceptable in most designs (hardware overhead of triple modular redundancy exceeds 200%). At circuit-level, traditional memory cells (SRAM bit- cells, latches, flip-flops) can be replaced with SER-tolerant cells. Various hardened storage cells have been proposed in the literature [3], [4]. The basic drawbacks of these cells are their cost (the area increase is generally close to duplication) and the fact that their hardening principle requires specific transistor sizing. As a result, these cells do not scale easily with typical device size shrinking. Scaling of feature sizes exarcebates the effects related to parameter variability and small width effects. SRAM Bit- cell layout will have a significant impact on these effects. Figure 1a presents a schematic diagram of a 6T memory bit cell. The trade-off for bit-cell designs must be balanced for best performance at the lowest cell size while keeping the highest yield. This leads to structured designs, more tolerant to process excursions and less sensitive to misalignment. This is obtained with the absence of bends in the diffusion regions of the transistors, and by placing all the poly lines in the same direction with minimal bulges. When cells are arrayed, all transistors see the same poly patterns; thus minimizing the poly proximity issues (Fig. 1b). (a) (b) Fig. 1 – (a) Schematic structure of 6T SRAM cell. (b) Layout as proposed in [5]. In this new scenario, most of the previously proposed SRAM hardening techniques that modify transistor sizes may significantly impact the final product reliability. For instance, the simple variation of the channel width or length of a given transistor (as in 10T hardened cells) may introduce bends in the diffusion or in the poly patterns causing designs more sensitive to misalignments. The purpose of this work is to analyze a possible SEU hardening technique based on individually selecting the threshold voltage of each transistor within the bit-cell. A similar technique was proposed to reduce the leakage consumption of SRAM memories [6]. This method improves cell hardness without changing layout regularity. The impact of this technique for other important parameters like access time and leakage currents are also investigated. An SRAM SEU Hardening Technique for Multi-Vt Nanometric CMOS Technologies G. Torrens, B. Alorda, S. Barceló, J. L. Rosselló, S. Bota and J. Segura Balearic Islands University (UIB), Palma de Mallorca (Spain), e-mail: gabriel.torrens@uib.es T