Journal of VLSI Signal Processing, 7, 7-16 (1994) c 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Self-Timed Logic Using Current-Sensing Completion Detection (CSCD) MARK E. DEAN, DAVID L. DILL, AND MARK HOROWITZ Computer Systems Laboratory, Stanford University, CA 94305 Received April 20, 1992; Revised September 15, 1992. Abstract. This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved perfor- mance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configura- tions are described and evaluated and transistor-level implementations are provided for comparison. 1. Introduction Self-timed logic provides a method for designing asyn- chronous logic circuits so that their correct behavior is independent of the speed of their components or signal wire delays. Self-timed or asynchronous digital systems can avoid many of the constraints which limit the performance and operating range of synchronous digital systems. Asynchronous digital systems can dynamically adapt their operating rate to match the sili- con’s process parameters and system’s environmental conditions. This adaptability allows asynchronous sys- tems to reliably operate over a wider range of temper- ature, voltage, and process conditions. By avoiding worst-case design constraints, required in most syn- chronous logic designs, asynchronous systems provide optimum silicon and system performance under all operating conditions. If all elements in a system are self-timed and interconnected via an asynchronous communication protocol, each element’s operating characteristic is isolated from the other system ele- ments. This allows each self-timed logic element to operate at maximum performance, independent of the other elements in the system. Seitz [ 1] gives an exten- sive discussion of self-timed logic and its advantages over globally clocked, or synchronous, logic. While most implementations of digital systems today are syn- chronous, self-timed asynchronous designs present an attractive alternative. Dual-rail signalling is one widely used style of self- timed circuit design. Every logical variable is encoded using two signal wires, called an encoding pair. 4- phase dual-rail uses three “logical” values: 0, 1, and Invalid. The protocol for 4-phase dual-rail signalling requires that the logical variable return to the invalid state after taking a 0 or 1 value. The invalid logic values serve as spacer tokens which separate the valid tokens in the data stream. This provides a means for the self- timed logic to detect completion of a logic function for each data token. Otherwise, it would not be possible to separate two consecutive tokens that happen to have the same value. Several methods of designing 4-phase dual-rail logic have been developed [1]-[5] [15] In these design styles the functional delay through a logic block for a spacer token is approximately the same as for a data token. Other 4-phase dual-rail design styles use a con- trol signal to reset, or precharge all gates in the func- tion block in parallel before accepting the next data token [6]-[8]. This type of precharged, dual-rail logic implementation reduces the delay required to process a spacer token. An alternative method for implementing self-timed logic is to use transition signalling. Transition signal- ssignal-ignal- ling is implemented such that a transition on wire Xi (i = 0, 1) of an encoding pair is interpreted as a new datum with value i. This removes the requirement of a spacer token between each valid data token. Unfor- tunately, it is difficult to implement functional units using transition signalling. Since each logic value en- coding is dependent on the code used for the previous token, a logic value can be represented by any of the