ICCAD95, pages 2-6 Efficient Validity Checking for Processor Verification Robert B. Jones , David L. Dill Computer Systems Laboratory, Stanford University, Stanford, CA 94305 Jerry R. Burch Cadence Berkeley Laboratories, Berkeley, CA 94704 Abstract We describe an efficient validity checker for the quantifier-free logic of equality with uninterpreted functions. This logic is well suited for verifyingmicroprocessor control circuitry since it allows the abstraction of datapath values and operations. Our validity checker uses special data structures to speed up case splitting, and powerful heuristics to reduce the number of case splits needed. In addition, we present experimental results and show that this implementation has enabled the automatic verification of an actual high- level microprocessor description. References [BD94a] V. Bhagwati and S. Devadas. Automatic verification of pipelined microprocessors. In 31st ACM/IEEE Design Automation Conference, 1994. [BD94b] J. R. Burch and D. L. Dill. Automatic verification of microprocessor control. In Computer Aided Verification. 6th International Conference, 1994. [Bea93] D. L. Beatty. A Methodology for Formal Hardware Verification with Application to Microprocessors. PhD thesis, School of Computer Science, Carnegie Mellon University, August 1993. [C+94] F. Corella et al. Multiway decision graphs for automated hardware verification. Unpublished manuscript, August 1994. [CLR90] T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. MIT Press, 1990. [Cyr93] D. Cyrluk. Microprocessor verification in PVS: A methodology and simple example. Technical Report SRI-CSL-93-12, SRI Computer Science Laboratory, December 1993. [HP90] J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach . Morgan Kaufmann, 1990. [K+94] J. Kuskin et al. The Stanford FLASH multiprocessor. In International Symposium on Computer Architecture (ISCA) , 1994. [LCDM89] P. Lammens, L. Claesen, and H. De Man. Correctness verification of VLSI modules supported by a very efficient boolean prover. In Proceedings: IEEE International Conference on Computer Design, October 1989. [Nel81] G.Nelson.Techniques for program verification.Technical Report CSL-81-10, Xerox PARC, June 1981. [NO79] G. Nelson and D. C. Oppen. Simplification by cooperating decision procedures. ACMTransactions on ProgrammingLanguagesand Systems,1(2):245–257, October 1979. [NO80] G. Nelson and D. C. Oppen. Fast decision procedures based on congruence closure. Journal of the ACM, 27(2):356– 364, April 1980. [SB90] M. Srivas and M. Bickford. Formal verification of a pipelined microprocessor. IEEE Software, 7(5):52– 64, September 1990. [Sho79] R. E. Shostak. A practical decision procedure for arithmetic with function symbols. Journal of the ACM, 26(2):351–360, April 1979. [SM95] M. Srivas and S. P. Miller. Applying formal verification to a commercial microprocessor. In Computer HardwareDescription Languages,August 1995. [Tar75] R. E. Tarjan. Efficiency of a good but not linear set union algorithm. Journal of the ACM, 22(2):215–225, 1975. [Wil95] R. Wilson. Verification feels strain. Electronic Engineering Times, (840):18–22, March 1995. [Win95] P. J. Windley. Formal modeling and verification of microprocessors. IEEE Transactions on Computers, 44(1):54–72, January 1995.