IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 6, JUNE 2005 1073 Characterizing the Effects of the PLL Jitter Due to Substrate Noise in Discrete-Time Delta-Sigma Modulators Payam Heydari, Member, IEEE Abstract—This paper investigates the impact of clock jitter in- duced by substrate noise on the performance of the oversampling modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25- m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models. Index Terms— modulator, jitter, oversampling datat con- verter, phase-locked loop (PLL), phase noise, substrate noise. I. INTRODUCTION O NE of the greatest challenges in the design of a system-on-a-chip (SOC) is the need to place sensi- tive analog circuits and large complex digital signal processing components on the same die. Due to the high-level of interac- tions between the noisy digital blocks with the noise-sensitive analog portion of the system through various propagation mechanisms it is highly possible that the large-signal switching transients of the digital circuits corrupt the performance of the analog sub-blocks. In an SOC, coupling from digital circuits into analog components mostly propagates through the common substrate, thereby being named as substrate noise. Substrate coupling degrades analog signal integrity in mixed-signal integrated circuits where thousands of digital gates may inject noise into the substrate, especially during clock transitions, introducing hundreds of millivolts of distur- bance in the substrate potential [1]–[4]. The peak amplitude and pulse-width of substrate noise is multiple orders of mag- nitude larger than those of device noise sources (e.g, thermal noise and -noise), thereby making substrate noise to be the dominant noise sources that influence the performance mixed analog–digital (A/D) integrated circuit. Manuscript received November 12, 2003; revised September 9, 2004. This paper was recommended by Associate Editor A. Ushida. The author is with the Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697-2625 USA (e-mail: payam@eecs.uci.edu). Digital Object Identifier 10.1109/TCSI.2005.849118 modulation is a ubiquitous technique widely used in mixed-signal integrated circuits to achieve high resolution systems including oversampling data converters [5]–[8], and frequency synthesizers [9]–[14]. Depending on the implemen- tation there are two types of modulators discrete-time (DT) [5], and continuous-time (CT) [15]. The more popular DT modulators, which are the focus of this paper, are less susceptible to noise than the CT counterparts and are easily implemented using switched capacitor circuits. Although numerous papers use the oversampling technique to design high-resolution systems that target various types of design criteria and applications [5], only a few papers study the effect of substrate noise on the performance of oversampling data converters. Blalack et al. in [16] presented an experimental study of the effects of switching noise in a high resolution over- sampling data converter. With the design of an experimental test circuit, the authors were able to make interesting observations about the temporal spacing of the noise clock transitions with respect to the sampling clock transitions and its impact on the signal-to-noise+distortion ratio (SNDR) of the converter. The authors, however, did not quantify their observations and exper- iments. Therefore, some of their experimental results are valid only for a particular architecture that was used in their ex- periments. [15] studies the performance degradation in CT modulator due to the clock jitter. The noise model used by [15] is inaccurate and this model is not properly incorporated in the behavioral model of the CT modulator. Demir et al. in [17] proposed a generalized methodology for the evaluation of the interference noise caused by the digital switching activity. The authors used Markov chains to model the digital switching activ- ities. The propagation media (e.g., substrate, the power-grid net- work) is modeled by a linear time-invariant (LTI) system. The methodology is very general and as a result, cannot address spe- cific problems in conjunction with the modulators. The goal of this paper is to consider the effects of substrate noise on the performance of the DT oversampling modula- tors. The main contributions of this paper are as follows: • an efficient stochastic model for substrate noise coupling in heavily doped substrates; • a new study on the effects of phase-locked loop (PLL) jitter induced by substrate noise in the performance of the DT modulators. Section II presents a general overview of modulators. Section III explains a new mathematical model for substrate noise. Next, a detailed analytical model for the PLL clock jitter 1057-7122/$20.00 © 2005 IEEE