IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 8, AUGUST 2004 1501 Interconnect Energy Dissipation in High-Speed ULSI Circuits Payam Heydari, Member, IEEE, Soroush Abbaspour, Student Member, IEEE, and Massoud Pedram, Fellow, IEEE Abstract—This paper presents a detailed empirical study and an- alytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing. This is in sharp con- trast with the steady-state analysis, which states that driver size has no impact on the energy dissipation per output change. In ad- dition, we propose a new design metric which is the product of en- ergy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay, and the percentage of maximum undershoot when the circuit exhibits an underdamped behavior. This metric is used during the driver sizing problem for- mulation for minimum energy-delay-ringing product. The experi- mental results carried out by HSPICE simulation verify the accu- racy of our models. Index Terms—CMOS driver, electromagnetic coupling, energy dissipation, interconnect, noise margin, transmission line. I. INTRODUCTION N EW advances in CMOS technologies have tremendously improved the integration capability and the speed of op- eration and reduced the amount of energy consumed per signal transition. Technology scaling with 30% reduction in minimum feature size per generation results in: 1) gate delay reduction by 30%; 2) doubling of the number of transistors that fit in the same silicon area; 3) energy reduction per transition by 30% to 65% depending on the degree of accompanying supply voltage scaling. These technology-induced improvements, coupled with advances in circuits and microarchitecture design, are expected to continue to support and to sustain the Moore’s law until year 2014 [1]. The wiring system of a 1-billion transistor die will de- liver signal and power to each transistor on the chip, provide low-skew and low-jitter clock to latches, flip-flops and dy- namic circuits, and also distribute data and control signals throughout the chip [2]. Providing the required global con- nectivity throughout the whole chip demands long on-chip wires. These global wires should deliver high frequency signals (presently at around 1–2 GHz) to various circuits. This implies Manuscript received August 23, 2002; revised March 5, 2003. This paper was recommended by Associate Editor P. Wambacq. P. Heydari is with the Department of Electrical and Computer Engi- neering, University of California, Irvine, CA 92697-2625 USA (e-mail: payam@ece.uci.edu). S. Abbaspour and M. Pedram are with the Department of Electrical Engi- neering Systems, University of Southern California, Los Angeles, CA 90089 USA. Digital Object Identifier 10.1109/TCSI.2004.832738 that the global wires exhibit transmission line effects including electromagnetic coupling. On the other hand, as technology sizes continue to decrease, many new effects are being observed due to the use of nanometer technologies. Some significant deep sub-quarter-micrometer effects are caused by increasing cross-coupling capacitance and coupling inductance. So far, the well-known model has been used as an inter- connect energy model, where includes the capacitance of the interconnect as well as the capacitances of driving and driven circuitries, and is the voltage swing. This model, however, fails to predict the interconnect energy dissipation in the current range of clock frequencies, where the signal transients do not settle to a steady-state value due to the small clock cycle-time. Moreover, this model does not consider coupling noise being imposed by neighboring wires as well as other transmission line properties. As we will see in this paper, these effects must be taken into account in the energy calculations, that will otherwise lead to erroneous results. An analytical interconnect energy model with consideration of event coupling has been proposed in [3]. The authors used nodal equations for a system of interconnects to obtain the state vector of the system. The state vectors were utilized in the interconnect energy dissipation expression. This approach does not capture the transmission line effects. It also assumes that the system reaches the steady state. In [4], authors showed that using distributed RC circuits do not capture all behaviors of lossy transmission lines that can be captured otherwise using the transmission line equations. Taylor et al. proposed a deep submicrometer (DSM) aware power estimation methodology using a three-wire lookup table [5]. The dissipated energy of each individual interconnect is computed considering capacitive coupling effects of the immediate adjacent wires. Using a detailed SPICE simulation of all possible types of transitions on a group of three adjacent wires, a three-wire lookup table was created. To obtain the total energy dissipation, the sum of energy dissipations of each individual interconnect was computed [5]. [5], however, does not consider the transient behavior of the interconnect in the energy calculations. In this paper, accurate expressions for the energy dissipa- tion of coupled interconnects are obtained while addressing the transmission line effects on the energy dissipations. We provide empirical evidence as well as detailed closed-form analytical expressions for the energy dissipation of a lossy transmission line which is driven by a CMOS inverter and is terminated by a CMOS load. We show that this circuit configuration exhibits behavior similar to a new RLC circuit topology, and therefore, it is possible to reduce energy dissipation at a given clock fre- quency by driver sizing. The effect of driver sizing is to change 1057-7122/04$20.00 © 2004 IEEE