Epitaxial Si-based tunnel diodes P.E. Thompson a ,*, K.D. Robarta, M.E. Twigg a , S.L. Rommel b , N. Jin b , P.R. Berger b , R. Lake c , A.C. Seabaugh d , P.R. Chi e , D.S. Simons e "Naval Research Laboratory, Washington, DC 20375-5347, USA bDepartment of Electrical and Computer Engineering, University of Delaware, Newark, DE 19716, USA cApplied Research Laboratory, Raytheon Systems Company, Dallas, TX 75243, USA dDepartment of Electrical Engineering, University of Notre Dame, Notre Dame, IN 46556, USA °National1nstitute of Standards and Technology, Gaithersburg, MD 20899, USA Abstract Tunneling devices in combination with transistors offer a way to extend the performance of existing technologies by increasing circuit speed and decreasing static power dissipation. We have investigated Si-based tunnel diodes grown using molecular beam epitaxy (MBE). The basic structure is a p + layer formed by B delta doping, an undoped spacer layer, and an n + layer formed by Sb delta doping. In the n-on-p configuration, low temperature epitaxy (300-370°C) was used to minimize the effect of dopant segregation and diffusion. In the p-on-n configuration, a combination of growth temperatures from 320 to 550°C was used to exploit the Sb segregation to obtain a low Sb concentration in the B-doped layer. Post-growth rapid thermal anneals for 1 min in the temperature interval between 600 and 825°C were required to optimize the device characteristics. J p , the peak current density, and the peak-to-valley current ratio (PVCR), were measured at room temperature. An n-on-p diode having a spacer layer composed of 4 nm Si o . 6 Ge o . 4 , bounded on either side by 1 nm Si, had a J p = 2.3 kA/cm 2 and PVCR = 2.05. A p-on-n tunnel diode with an 8 nm Si spacer (5 nm grown at 320°C, 3 nm grown at 550°C) had a J p = 2.6 kA/cm 2 and PVCR = 1.7. Keywords: Tunnel diodes; Epitaxy; Delta doping; Silicon; Silicon-germanium 1. Introduction Since tunnel diodes were first reported by Esaki [1], there have been numerous attempts to exploit their intrinsically fast switching speed and negative differen- tial resistance (NDR) in circuits to increase speed, reduce standby current, and minimize device count. For example, it has been demonstrated that a standard six transistor complementary metal oxide Si (CMOS) static random access memory (SRAM) cell could be replaced with a cell composed of one transistor, a * Corresponding author. Tel.: +1-202-404-8541; fax: +1-202-404- 7194. E-mail address:thompson@estd.nrl.navy.mil(P.E. Thompson). capacitor, and two tunnel diodes, reducing the device area by a factor of 2.2 and decreasing the standby current by a factor of 8 [2]. Progress in this area has been limited by two primary factors. While Si Esaki tunnel diodes, based on a degenerately doped pin junction, have reported peak-to-valley current ratios (PVCR) > 4, the lack of an epitaxial formation process prevents easy integration with CMOS. The second fac- tor is low PVCR in Si tunnel diode configurations which are integrable with CMOS. The band offsets between Si and Si1-XGe X are inadequate for significant room temperature NDR in a resonant tunnel diode (RID). Hole RIDs have not been reported to have NDR above a temperature of 77 K [3-8]. The electron RTD reported by Ismail [9] had a PVCR of 1.2 at 300 K, but a thick (> 1 !-Lm) relaxed SiGe buffer layer is