INVITED PAPER Device and Architecture Outlook for Beyond CMOS Switches Many new devices that are being studied as replacements for CMOS are discussed in this paper; early results for benchmarking and performance comparison are presented for some of the devices. By Kerry Bernstein, Fellow IEEE , Ralph K. Cavin, III, Life Fellow IEEE , Wolfgang Porod, Fellow IEEE , Alan Seabaugh, Fellow IEEE , and Jeff Welser, Senior Member IEEE ABSTRACT | Sooner or later, fundamental limitations destine complementary metal–oxide–semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale struc- tures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these novel switches can complement the execution of specific algorithms or workloads by enabling quite unique architectures. Ultimately, exploiting these unusual responses will extend throughput in high-performance com- puting. Alternative tokens also require new transport mechan- isms to replace the conventional chip wire interconnect schemes of charge-based computing. New intrinsic limits to scaling in post-CMOS technologies are likely to be bounded ultimately by thermodynamic entropy and Shannon noise. KEYWORDS | Nanoarchitectures; nanomagnet logic; post- complementary metal–oxide–semiconductor (CMOS); pseudos- pin; quantum-dot cellular-automata architectures (QCAs); quantum-dot cellular automata; spin; tunnel field-effect tran- sistor (TFET); tunneling I. MOTIVATION It has been estimated that information technology (IT) producing and intensive IT-using industries currently ac- count for over a quarter of the U.S. Gross Domestic Product (GDP), and drive 50% of this country’s eco- nomic growth [1]. The unprecedented growth of the IT industry has largely been due to the exponential increase in the performance of the semiconductor chips that are at the heart of all modern electronics. The key compo- nent on these chips is the complementary metal–oxide– semiconductor (CMOS) field-effect transistor (FET), and the ability to scale these devices to ever-smaller dimen- sions has been the primary driver of this increased performance. For over 30 years, the industry has been able to pack twice as many FETs onto a chip every 18– 24 months, in what has come to be known as BMoore’s law[ [2]. This has resulted in an exponential increase in the information processing capability per unit area on the chipVor more importantly, per dollar. This has meant not only that existing chip-based products get faster and/or cheaper each year, but also has expanded the number of products that use semiconductor chips to increase func- tionality, from toasters to cell phones to supercomputers. The rules for FET scaling that have enabled this revolution were outlined by Dennard et al. in the early Manuscript received February 3, 2010; accepted May 24, 2010. Date of publication October 4, 2010; date of current version November 19, 2010. This work was supported in part by the Semiconductor Research Corporation, Nanoelectronics Research Institute (SRC-NRI) including the member companies the National Institute of Standards and Technology (NIST) and the National Science Foundation (NSF). K. Bernstein is with IBM T. J. Watson Research Center, Yorktown Heights, NY USA (e-mail: kbernstein@us.ibm.com). R. K. Cavin, III is with the Semiconductor Research Corporation, Durham, NC 27707 USA (e-mail: cavin@src.org). W. Porod and A. Seabaugh are with the University of Notre Dame, Notre Dame, IN 46556 USA (e-mail: porod@nd.edu; seabaugh.1@nd.edu). J. Welser is with the IBM Almaden Research Center, San Jose, CA 95120-6099 USA and with the Semiconductor Research Corporation, Durham, NC 27707 USA (e-mail: jeff.welser@src.org). Digital Object Identifier: 10.1109/JPROC.2010.2066530 Vol. 98, No. 12, December 2010 | Proceedings of the IEEE 2169 0018-9219/$26.00 * 2010 IEEE